8V19N408 synthesizer equivalent, femtoclock ng jitter attenuator and clock synthesizer.
* Core timing unit for JESD204B wireless infrastructure clocks
* Fourth generation FemtoClock® NG technology
* First stage PLL uses an external VCXO for jitte.
* Three independent output clock frequency dividers N (range of ÷1
to ÷96)
* Clock output frequency range (VC0-0.
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