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9DBL0252 - 2-output 3.3V PCIe Zero-Delay Buffer

Download the 9DBL0252 datasheet PDF. This datasheet also covers the 9DBL0242 variant, as both devices belong to the same 2-output 3.3v pcie zero-delay buffer family and are provided as variant models within a single manufacturer datasheet.

General Description

The 9DBL0242 / 9DBL0252 devices are 3.3V members of IDT's Full-Featured PCIe family.

The devices support PCIe Gen1-4 Common Clocked (CC) and PCIe Gen2 Separate Reference Independent Spread (SRIS) systems.

Key Features

  • 2.
  • 1-200 MHz Low-Power (LP) HCSL DIF pairs.
  • 9DBL0242 default ZOUT = 100.
  • 9DBL0252 default ZOUT = 85.
  • 9DBL02P2 factory programmable defaults.
  • Easy AC-coupling to other logic families, see IDT.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (9DBL0242-IDT.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 9DBL0252
Manufacturer IDT
File Size 293.48 KB
Description 2-output 3.3V PCIe Zero-Delay Buffer
Datasheet download datasheet 9DBL0252 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
2-output 3.3V PCIe Zero-Delay Buffer 9DBL0242 / 9DBL0252 DATASHEET Description The 9DBL0242 / 9DBL0252 devices are 3.3V members of IDT's Full-Featured PCIe family. The devices support PCIe Gen1-4 Common Clocked (CC) and PCIe Gen2 Separate Reference Independent Spread (SRIS) systems. It offers a choice of integrated output terminations providing direct connection to 85 or 100 transmission lines. The 9DBL02P2 can be factory programmed with a user-defined power up default SMBus configuration.