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9DBL0453 Datasheet

4-output 3.3V LP-HCSL Zero-Delay Buffer

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4-output 3.3V LP-HCSL Zero-Delay
Buffer with LOS Indicator
9DBL04x3
Datasheet
General Description
The 9DBL04x3 devices are 3.3V members of IDT's Full-Featured
PCIe clock family. They support PCIe Gen1-4 Common Clock (CC)
architectures and also support NVLINK applications. The 9DBL04x3
parts have a Loss of Signal (LOS) indicator to support fault-tolerant,
high reliability systems.
Recommended Application
PCIe Gen1-4 and NVLINK clock distribution for Riser Cards,
Storage, Networking, JBOD, Communications, Access Points
Output Features
Loss Of Signal (LOS) open drain output
4 – 1-200 MHz Low-Power (LP) HCSL DIF pairs
9DBL0443 default Zout = 100
9DBL0453 default Zout = 85
Easy AC-coupling to other logic families, see IDT application note
AN-891.
Key Specifications
PCIe Gen1-4 CC compliant in ZDB or fanout buffer mode
Supports NVLINK at 156.25M in ZDB or fanout buffer mode
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew < 50ps
Bypass mode additive phase jitter is 0 ps typical rms for PCIe
Bypass mode additive phase jitter 160fs rms typ. @ 156.25M
(1.5M to 10M)
Block Diagram
Features/Benefits
LOS indicator signals loss of input clock; adds fault tolerance,
eases system diagnostics
Direct connection to 100(xx43) or 85(xx53) transmission
lines; saves 8 resistors compared to standard PCIe devices
134mW typical power consumption in PLL mode; eliminates
thermal concerns
OE# pin for each DIF output; support DIF power management
HCSL-compatible differential input; can be driven by common
clock sources
Spread Spectrum tolerant; allows reduction of EMI
Outputs blocked until PLL is locked; clean system start-up
Pin/SMBus selectable PLL bandwidth and PLL Bypass; minimize
phase jitter for each application
Device contains default configuration; SMBus interface not
required for device operation
3 selectable SMBus addresses; multiple devices can easily share
an SMBus segment
SMBus-selectable features allows optimization to customer
requirements:
control input polarity
control input pull up/downs
slew rate for each output
differential output amplitude
output impedance for each output
Contact IDT for quick-turn customization of SMBus defaults;
allows exact optimization to customer requirements
Space saving 32-pin 5 × 5mm VFQFPN; minimal board space
vOE(3:0)#
4
CLK_IN
CLK_IN#
vSAD R_ tri
^vH IBW_ BYPM_ L OBW #
^C KPW RGD_ PD#
SDATA_3.3
SCLK_3.3
SS
C o mpa tib le
PLL
LOS
Logic
D IF3
4 Outputs
D IF0
L OS
©2017 Integrated Device Technology, Inc
1
February 1, 2017


Integrated Device Technology Electronic Components Datasheet

9DBL0453 Datasheet

4-output 3.3V LP-HCSL Zero-Delay Buffer

No Preview Available !

Pin Configuration
9DBL04x3 Datasheet
^vHIBW_BYPM_LOBW# 1
FB_DNC 2
FB_DNC# 3
VDDR3.3 4
CLK_IN 5
CLK_IN# 6
NC 7
GNDDIG 8
32 31 30 29 28 27 26 25
9DBL0443
9DBL0453
connect epad to
GND
9 10 11 12 13 14 15 16
24 vOE2#
23 DIF2#
22 DIF2
21 LOS
20 VDDA3.3
19 vOE1#
18 DIF1#
17 DIF1
32-pin VFQFPN, 5x5 mm, 0.5mm pitch
^ prefix indicates internal 120KOhm pull up resistor
^v prefix indicates internal 120KOhm pull up AND pull down resistor (biased
to VDD/2)
v prefix indicates internal 120KOhm pull down resistor
Power Management Table
CKPW RGD_PD#
CLK_I N
SMBus
OE bit
OEx# Pin
0 X XX
1
Running
1
0
1
Running
1
1
1
Running
0
X
1. The output state is set by B11[1:0] (Low/Low default)
2. Input polarities defined as default values for xx43/xx53 devices.
3. If Bypass mode is selected, the PLL will be off, and outputs will be running.
DI Fx/DI Fx#
True O/P
Comp. O/P
Low1
Low1
Running
Running
Disabled1
Disabled1
Disabled1
Disabled1
PLL
Off
On3
On3
On3
SMBus Address Selection Table
State of SADR on first application of
CKPWRGD_PD#
SADR
0
M
1
Address
1101011
1101100
1101101
+ Read/Write bit
x
x
x
Note: If not using CKPWRGD (CKPWRGD tied to VDD3.3), all 3.3V VDD need to transition from 2.1V to 3.135V
in <300µsec.
PLL Operating Mode Table
HiBW_BypM_
LoBW#
MODE
Byte1 [7:6]
Readback
0
PLL Lo BW
00
M
Bypass
01
1
PLL Hi BW
11
Byte1 [4:3]
Control
00
01
11
Power Connections
Pin Number
VDD GND
4 33
11 8
15, 25
33
20 33
Description
Input receiver analog
Digital Power
DIF outputs
PLL Analog
©2017 Integrated Device Technology, Inc
2
February 1, 2017


Part Number 9DBL0453
Description 4-output 3.3V LP-HCSL Zero-Delay Buffer
Maker IDT
PDF Download

9DBL0453 Datasheet PDF





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