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ICS514 Datasheet

PLL CLOCK GENERATOR

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LOCO™ PLL CLOCK GENERATOR
DATASHEET
ICS514
Description
The ICS514 LOCOTM is the most cost effective way to
generate a high-quality, high-frequency clock output
from a 14.31818 MHz crystal or clock input. The name
LOCO stands for Low Cost Oscillator, as it is designed
to replace crystal oscillators in most electronic
systems. Using Phase-Locked Loop (PLL) techniques,
the device uses a standard, inexpensive crystal to
produce output clocks up to 66.66 MHz.
Stored in the chip’s ROM is the ability to generate five
different output frequencies, allowing one chip to work
in different speed processor systems.
The device also has a power-down mode that turns off
the clock outputs when both select pins are low. In this
mode, the internal PLL is not running.
Block Diagram
Features
Packaged as 8-pin SOIC or die
Pb (lead) free package
IDT’s lowest cost PLL clock plus reference
Produces common computer frequencies
Input crystal frequency typically 14.3182 MHz
Output clock frequencies up to 66.66 MHz from a
14.3182 MHz crystal or input clock
Low jitter of 50 ps (one sigma)
Compatible with all popular CPUs
Duty cycle of 45/55
Custom frequencies available
Operating voltage of 3.3 V to 5.5 V
Power-down mode turns off chip
25 mA drive capability at TTL levels
Advanced, low-power CMOS process
VDD
S1:0 2
X1/ICLK
14.31818 MHz crystal
or clock input
X2
Crystal
Oscillator
Optional crystal capacitors
PLL Clock
Synthesis
and Control
Circuitry
GND
CLK
REF
IDT™ / ICS™ LOCO™ PLL CLOCK GENERATOR
1
ICS514
REV G 051310


Integrated Device Technology Electronic Components Datasheet

ICS514 Datasheet

PLL CLOCK GENERATOR

No Preview Available !

ICS514
LOCO™ PLL CLOCK GENERATOR
CLOCK MULTIPLIER
Pin Assignment
X1/ICLK
VDD
GND
REF
1
2
3
4
8 X2
7 S1
6 S0
5 CLK
8-pi n (150 mi l ) SOI C
Clock Decoding Table (MHz) with 14.31818
MHz Crystal or Clock Input
S1 S0
CLK
0 0 Power-down CLK
01
25
M0
33.33
M1
40
10
50
11
66.66
Multiplier
1.746
2.328
2.794
3.492
4.656
Accuracy
1 ppm
0.008%
1 ppm
1 ppm
0.008%
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (floating)
CLK and REF stop low in power-down state
Pin Descriptions
Pin Pin
Number Name
1 XI/ICLK
2 VDD
3 GND
4 REF
5 CLK
6 S0
7 S1
8 X2
Pin
Type
Input
Power
Power
Output
Output
Tri-level Input
Tri-level Input
Output
Pin Description
Crystal connection to a 14.31818 MHz crystal or clock input.
Connect to +3.3 V or +5 V.
Connect to ground.
Reference 14.31818 MHz crystal oscillator buffered clock output.
Clock output per table above.
Select 0 for output clock. Connect to GND or VDD or float. See
table above.
Select 1 for output clock. Connect to GND or VDD or float. See
table above.
Crystal connection to a 14.31818 MHz crystal. Leave unconnected
for clock input.
Notes:
1. With S1 = S0 = 0, the internal PLL is turned off and the CLK outputs stops low. The crystal oscillator and
REF output are still active.
2. With a clock input, the phase relationship between the input and the output clocks can change each time
the device is powered on. If a fixed phase relationship is required, use the ICS571 or other zero delay
multipliers.
IDT™ / ICS™ LOCO™ PLL CLOCK GENERATOR
2
ICS514
REV G 051310


Part Number ICS514
Description PLL CLOCK GENERATOR
Maker IDT
Total Page 7 Pages
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