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ICS542 Datasheet

CLOCK DIVIDER

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CLOCK DIVIDER
DATASHEET
ICS542
Description
The ICS542 is cost effective way to produce a high-quality
clock output divided from a clock input. The chip accepts a
clock input up to 156 MHz at 3.3 V and produces a divide by
2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs
on the chip, one being a low-skew divide by two of the other.
For instance, if an 100 MHz input clock is used, the ICS542
can produce low-skew 50 MHz and 25 MHz clocks, or low
skew 25 MHz and 12.5 MHz clocks. The chip has an
all-chip power-down mode that stops the outputs low, and
an OE pin that tri-states the outputs.
See the ICS541 and ICS543 for other clock dividers, and
the ICS501, 502, 511, 512, and 525 for clock multipliers.
Features
8-pin SOIC package, Pb free
Available in RoHS compliant package
IDT’s lowest cost clock divider
Low skew (500 ps) outputs. One is /2 of the other
Easy to use with other generators and buffers
Input clock frequency up to 156 MHz
Output clock duty cycle of 45/55
Power-down turns off chip
Output Enable
Advanced, low-power CMOS process
Operating voltage of 3.3 V or 5 V
Does not degrade phase noise - no PLL
Available in industrial and commercial temperature
ranges
Block Diagram
VDD
S1, S0
Input Clock
Divider
and
Selection
Circuitry
/2
CLK1
CLK2
GND
OE (both outputs)
IDT™ / ICS™ CLOCK DIVIDER
1
ICS542
REV J 051310


Integrated Device Technology Electronic Components Datasheet

ICS542 Datasheet

CLOCK DIVIDER

No Preview Available !

ICS542
CLOCK DIVIDER
Pin Assignment
I CLK
VDD
GND
S0
1
2
3
4
8 CLK
7 CLK/2
6 OE
5 S1
8-pin (150 mil) SOIC
CLOCK DIVIDER
Clock Decoding Table
S1 S0
CLK
CLK/2
00
Power Down All
01
Input/6
Input/12
10
Input/8
Input/16
11
Input/2
Input/4
0 = connect directly to ground
1 = connect directly to VDD
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
ICLK
VDD
GND
S0
S1
OE
CLK/2
CLK
Pin
Type
XI
Power
Power
Input
Input
Input
Output
Output
Pin Description
Clock input.
Connect to +3.3 V or +5 V.
Connect to ground.
Select 0 for output clock. Connect to GND or VDD, per decoding table above.
Internal pull-up resistor.
Select 1 for output clock. Connect to GND or VDD, per decoding table above.
Internal pull-up resistor.
Output Enable. Tri-states both output clocks when low. Internal pull-up
resistor.
Clock output per table above. Low skew divide by two of pin 8 clock.
Clock output per table above.
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50trace (a commonly
used trace impedance), place a 33resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20.
Decoupling Capacitor
As with any high-performance mixed-signal IC, the ICS542
must be isolated from system power supply noise to perform
optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) To minimize EMI, the 33series termination resistor (if
needed) should be placed close to the clock output.
3) An optimum layout is one with all components on the
IDT™ / ICS™ CLOCK DIVIDER
2
ICS542
REV J 051310


Part Number ICS542
Description CLOCK DIVIDER
Maker IDT
Total Page 6 Pages
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