ICS571 Datasheet PDF - IDT LOW PHASE NOISE ZERO DELAY BUFFER Specs

ICS571 - LOW PHASE NOISE ZERO DELAY BUFFER

Datasheet Summary

Description

The ICS571 is a high speed, high output drive, low phase noise Zero Delay Buffer (ZDB) which integrates IDT’s proprietary analog/digital Phase Locked Loop (PLL) techniques.

IDT introduced the world standard for these devices in 1992 with the debut of the AV9170, and updated that with the ICS570.

Features

Packaged in 8-pin SOIC (Pb free).
Can function as low phase noise x2 multiplier.
Low skew outputs. One is ÷2 of other.
Input clock frequency up to 160 MHz at 3.3 V.
Phase noise of better than -100 dBc/Hz from 1 kHz to 1 MHz offset from carrier.
Can recover poor input clock duty cycle.
Output clock duty cycle of 45/55 at 3.3 V.
High drive strength for >100 MHz outputs.
Full CMOS clock swings with 25 mA drive capabil.

Datasheet Details

Part number	ICS571
Manufacturer	IDT
File Size	136.08 KB
Description	LOW PHASE NOISE ZERO DELAY BUFFER
Datasheet	ICS571 Datasheet
Additional preview pages of the ICS571 datasheet.

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Full PDF Text Transcription

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LOW PHASE NOISE ZERO DELAY BUFFER DATASHEET ICS571 Description The ICS571 is a high speed, high output drive, low phase noise Zero Delay Buffer (ZDB) which integrates IDT’s proprietary analog/digital Phase Locked Loop (PLL) techniques. IDT introduced the world standard for these devices in 1992 with the debut of the AV9170, and updated that with the ICS570. The ICS571, part of IDT’s ClockBlocks™ family, was designed to operate at higher frequencies, with faster rise and fall times, and with lower phase noise. The zero delay feature means that the rising edge of the input clock aligns with the rising edges of both outputs, giving the appearance of no delay through the device. There are two outputs on the chip, one being a low-skew divide by two of the other.

Published: Apr 5, 2019 |