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ICS571 - Low Phase Noise Zero Delay Buffer

General Description

The ICS571 is a high speed, high output drive, low phase noise Zero Delay Buffer (ZDB) which integrates ICS’ proprietary analog/digital Phase Locked Loop (PLL) techniques.

ICS introduced the world standard for these devices in 1992 with the debut of the AV9170, and updated that with the ICS570.

Key Features

  • Packaged in 8 pin SOIC.
  • Can function as low phase noise x2 multiplier.
  • Low skew outputs. One is ÷2 of other.
  • Input clock frequency up to 160 MHz at 3.3V.
  • Phase noise of better than -100 dBc/Hz from 1kHz to 1MHz offset from carrier.
  • Can recover poor input clock duty cycle.
  • Output clock duty cycle of 45/55 at 3.3V.
  • High drive strength for >100 MHz outputs.
  • Full CMOS clock swings with 25mA drive capability at T.

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Datasheet Details

Part number ICS571
Manufacturer Integrated Circuit Systems
File Size 85.70 KB
Description Low Phase Noise Zero Delay Buffer
Datasheet download datasheet ICS571 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com PRELIMINARY INFORMATION ICS571 Low Phase Noise Zero Delay Buffer Features • Packaged in 8 pin SOIC. • Can function as low phase noise x2 multiplier. • Low skew outputs. One is ÷2 of other. • Input clock frequency up to 160 MHz at 3.3V. • Phase noise of better than -100 dBc/Hz from 1kHz to 1MHz offset from carrier • Can recover poor input clock duty cycle. • Output clock duty cycle of 45/55 at 3.3V. • High drive strength for >100 MHz outputs. • Full CMOS clock swings with 25mA drive capability at TTL levels. • Advanced, low power CMOS process. • Operating voltages of 3.0 to 5.5 V. Description The ICS571 is a high speed, high output drive, low phase noise Zero Delay Buffer (ZDB) which integrates ICS’ proprietary analog/digital Phase Locked Loop (PLL) techniques.