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ICS570A - Multiplier and Zero Delay Buffer

General Description

The ICS570A is a high performance Zero Delay Buffer (ZDB) which integrates ICS’ proprietary analog/digital Phase Locked Loop (PLL) techniques.

ICS introduced the world standard for these devices in 1992 with the debut of the AV9170.

Key Features

  • Packaged in 8 pin SOIC.
  • Pin-for-pin replacement and upgrade to ICS570.
  • Functional equivalent to AV9170 (not a pinfor-pin replacement).
  • Low input to output skew of 500 ps max.
  • Low skew (250 ps) outputs. One is ÷ 2 of other.
  • Ability to choose between 14 different multipliers from 0.5X to 32X.
  • Input clock frequency up to 150 MHz at 3.3V.
  • Can recover poor input clock duty cycle.
  • Output clock duty cycle of 45/55.

📥 Download Datasheet

Datasheet Details

Part number ICS570A
Manufacturer Integrated Circuit Systems
File Size 108.68 KB
Description Multiplier and Zero Delay Buffer
Datasheet download datasheet ICS570A Datasheet

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www.DataSheet4U.com ICS570A Multiplier and Zero Delay Buffer Description The ICS570A is a high performance Zero Delay Buffer (ZDB) which integrates ICS’ proprietary analog/digital Phase Locked Loop (PLL) techniques. ICS introduced the world standard for these devices in 1992 with the debut of the AV9170. The ICS570A, part of ICS’ ClockBlocks™ family, was designed as a performance upgrade to meet today’s higher speed and lower voltage requirements. The zero delay feature means that the rising edge of the input clock aligns with the rising edges of both outputs, giving the appearance of no delay through the device. There are two outputs on the chip, one being a low-skew divide by two of the other.