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ICS570 - MULTIPLIER AND ZERO DELAY BUFFER

Datasheet Summary

Description

The ICS570 is a high-performance Zero Delay Buffer (ZDB) which integrates IDT’s proprietary analog/digital Phase Locked Loop (PLL) techniques.

The A version is recommended for 5 V designs and the B version for 3.3 V designs.

Features

  • 8-pin SOIC package.
  • Available in Pb (lead) free package.
  • Pin-for-pin replacement and upgrade to ICS570M.
  • Functional equivalent to AV9170 (not a pin-for-pin replacement).
  • Low input to output skew of 300 ps max (>60 MHz outputs).
  • Ability to choose between 14 different multipliers from 0.5x to 32x.
  • Output clock frequency up to 170 MHz at 3.3 V.
  • Can recover degraded input clock duty cycle.
  • Output clock duty cycle of 45.

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Datasheet preview – ICS570

Datasheet Details

Part number ICS570
Manufacturer Renesas
File Size 374.31 KB
Description MULTIPLIER AND ZERO DELAY BUFFER
Datasheet download datasheet ICS570 Datasheet
Additional preview pages of the ICS570 datasheet.

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Full PDF Text Transcription

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MULTIPLIER AND ZERO DELAY BUFFER DATASHEET ICS570 Description The ICS570 is a high-performance Zero Delay Buffer (ZDB) which integrates IDT’s proprietary analog/digital Phase Locked Loop (PLL) techniques. The A version is recommended for 5 V designs and the B version for 3.3 V designs. The chip is part of IDT’s ClockBlocksTM family, and was designed as a performance upgrade to meet today’s higher speed and lower voltage requirements. The zero delay feature means that the rising edge of the input clock aligns with the rising edges of both output clocks, giving the appearance of no delay through the device. There are two outputs on the chip, one being a low-skew divide by two of the other output.
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