ICS673-01 - PLL BUILDING BLOCK

IDT

Description

The ICS673-01 is a low cost, high performance Phase Locked Loop (PLL) designed for clock synthesis and synchronization.

Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO), and two output buffers.

One output buffer is a divide by two of the other.

Packaged in 16 pin SOIC (Pb-free, ROHS compliant).
Access to VCO input and feedback paths of PLL.
VCO operating range up to 120 MHz (5V).
Able to lock MHz range outputs to kHz range inputs through the use of external dividers.
Output Enable tri-states outputs.
Low skew output clocks.
Power Down turns off chip.
VCO predivide to feedback divider of 1 or 4.
25 mA output drive capability at TTL levels.
Advance.

Part Number	Description	Manufacturer
ICS670-01	LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER	Renesas
ICS670-03	LOW PHASE NOISE ZERO-DELAY BUFFER/MULTIPLIER	Renesas
ICS671-01	ZERO DELAY LOW SKEW BUFFER/MULTIPLIER	Renesas
ICS671-03	LOW SKEW BUFFER	Renesas
ICS671-06	Low Skew Buffer	Integrated Circuit Systems

Part Number	Description
ICS670-01	LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER
ICS670-02	LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER
ICS670-03	LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER
ICS670-04	LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER
ICS674-01	USER CONFIGURABLE DIVIDER

Published: Jun 4, 2020 |