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Integrated Device Technology Electronic Components Datasheet

ICS673-01 Datasheet

PLL BUILDING BLOCK

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ICS673-01
PLL BUILDING BLOCK
Description
The ICS673-01 is a low cost, high performance Phase
Locked Loop (PLL) designed for clock synthesis and
synchronization. Included on the chip are the phase
detector, charge pump, Voltage Controlled Oscillator
(VCO), and two output buffers. One output buffer is a
divide by two of the other. Through the use of external
reference and VCO dividers (the ICS674-01), the user
can customize the clock to lock to a wide variety of
input frequencies.
The ICS673-01 also has an output enable function that
puts both outputs into a high-impedance state. The
chip also has a power down feature which turns off the
entire device.
For applications that require low jitter or jitter
attenuation, see the MK2069. For a smaller package,
see the ICS663.
Features
Packaged in 16 pin SOIC (Pb-free, ROHS compliant)
Access to VCO input and feedback paths of PLL
VCO operating range up to 120 MHz (5V)
Able to lock MHz range outputs to kHz range inputs
through the use of external dividers
Output Enable tri-states outputs
Low skew output clocks
Power Down turns off chip
VCO predivide to feedback divider of 1 or 4
25 mA output drive capability at TTL levels
Advanced, low power, sub-micron CMOS process
Single supply +3.3 V or +5 V ±10% operating voltage
Industrial temperature range available
Forms a complete PLL, using the ICS674-01
For better jitter performance, please use the MK1575
Block Diagram
Clock Input
REFIN
FBIN
PD
(entire chip)
VDD
CHCP VCOIN
2
VDD
Phase/
Frequency
Detector
Icp
UP
DOWN
VCO
Icp
2
1
MUX
40
3
CAP GND
SEL
External Feedback Divider
(such as the ICS674-01)
2
OE (both
outputs)
CLK1
CLK2
MDS 673-01 L
1
www.idt.com
Revision 051310


Integrated Device Technology Electronic Components Datasheet

ICS673-01 Datasheet

PLL BUILDING BLOCK

No Preview Available !

ICS673-01
PLL BUILDING BLOCK
Pin Assignment
F B IN
VDD
VDD
GND
GND
GND
CHGP
VC O IN
1
2
3
4
5
6
7
8
16 R EFIN
15 NC
14 CLK1
13 CLK2
12 PD
11 SEL
10 OE
9 CAP
VCO Predivide Select Table
SEL
0
1
VCO Predivide
4
1
0 = connect pin directly to ground
1 = connect pin directly to VDD
16 pin narrow (150 m il) S O IC
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
FBIN
VDD
VDD
GND
GND
GND
CHGP
VCOIN
CAP
OE
SEL
PD
CLK2
CLK1
NC
REFIN
Pin
Type
Pin Description
Input Feedback clock input. Connect the feedback clock to this pin. Falling
edge triggered.
Power Connect to +3.3 V or +5 V and to VDD on pin 3.
Power Connect to VDD on pin 2.
Power Connect to ground.
Power Connect to ground.
Power Connect to ground.
Output Charge pump output. Connect to VCOIN under normal operation.
Input Input to internal VCO.
Input Loop filter return.
Input Output enable. Active when high. Tri-states both outputs when low.
Input Select pin for VCO predivide to feedback divider per table above.
Input Power down. Turns off entire chip when pin is low. Outputs stop low.
Output Clock output 2. Low skew divide by two version of CLK1.
Output Clock output 1.
- No connect. Nothing is connected internally to this pin.
Input Reference input. Connect reference clock to this pin. Falling edge is
triggered.
MDS 673-01 L
2
www.idt.com
Revision 051310


Part Number ICS673-01
Description PLL BUILDING BLOCK
Maker IDT
Total Page 3 Pages
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