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ICS831721I Datasheet

Differential Clock/Data Multiplexer

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Differential Clock/Data Multiplexer
ICS831721I
DATASHEET
General Description
The ICS831721I is a high-performance, differential HCSL clock/data
multiplexer and fanout buffer. The device is designed for the
multiplexing of high-frequency clock and data signals. The device has
two differential, selectable clock/data inputs. The selected input
signal is output at one differential HCSL output. Each input pair
accepts HCSL, LVDS, and LVPECL levels. The ICS831721I is
characterized to operate from a 3.3V power supply. Guaranteed
input, output-to-output and part-to-part skew characteristics make
the ICS831721I ideal for those clock and data distribution
applications demanding well-defined performance and repeatability.
The ICS831721I supports the clock multiplexing and distribution of
PCI Express Generation 1, 2 and 3 clock signals.
Features
2:1 differential clock/data multiplexer with fanout
Two selectable, differential inputs
Each differential input pair can accept the following levels: HCSL,
LVHSTL, LVDS and LVPECL
One differential HCSL output
Maximum input/output clock frequency: 700MHz (maximum)
Maximum input/output data rate: 1400Mb/s (NRZ)LVCMOS
interface levels for all control inputs
Input skew: 55ps (maximum)
Part-to-part skew: 400ps (maximum)
Full 3.3V supply voltage
Available in lead-free (RoHS 6) 16 TSSOP package
-40°C to 85°C ambient operating temperature
Block Diagram
IREF
CLK0
nCLK0
CLK1
nCLK1
Pulldown
Pullup/down
Pulldown
Pullup/down
SEL
nOE
Pulldown
Pullup/down
0
1
Pin Assignment
CLK0 1 16 IREF
nCLK0 2 15 SEL
VDD 3
14 VDD
CLK1 4 13 nQ
nCLK1 5 12 Q
GND 6
11 VDD
Q nc 7 10 GND
nQ
VDD 8
9 nOE
ICS831721I
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
ICS831721AGI REVISION A FEBRUARY 3, 2014
1
©2014 Integrated Device Technology, Inc.


Integrated Device Technology Electronic Components Datasheet

ICS831721I Datasheet

Differential Clock/Data Multiplexer

No Preview Available !

ICS831721I Data Sheet
DIFFERENTIAL CLOCK/DATA MULTIPLEXER
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1
Name
CLK0
Type
Input
Pulldown
Description
Non-inverting clock/data input 0.
2
3, 8, 11, 14
4
5
6, 10
nCLK0
VDD
CLK1
nCLK1
GND
Input
Power
Input
Input
Power
Pullup/Pulldown Inverting differential clock input 0. VDD/2 default when left floating.
Positive power supply.
Pulldown Non-inverting clock/data input 1.
Pullup/Pulldown Inverting differential clock input 1. VDD/2 default when left floating.
Power supply ground.
7
9
12, 13
15
nc
nOE
Q, nQ
SEL
Unused
Input
Output
Input
Pullup
Pulldown
No connect.
Output enable. See Table 3A for function. LVCMOS/LVTTL interface levels.
Differential output pair. HCSL interface levels.
Input select. See Table 3B for function. LVCMOS/LVTTL interface levels.
16
IREF
Input
An external fixed precision resistor (475) from this pin to ground provides a
reference current used for the differential current-mode Q, nQ outputs.
NOTE: Pullup and pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
RPULLDOWN
RPULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
Function Tables
Table 3A. nOE Configuration Table
Input
nOE
Operation
0 Output Q, nQ is enabled.
1 (default)
Output Q, nQ is in a high-impedance state.
NOTE: nOE is an asynchronous control.
Table 3B. SEL Configuration Table
Input
SEL Selected Input
0 (default)
CLK0, nCLK0
1 CLK1, nCLK1
NOTE: SEL is an asynchronous control.
ICS831721AGI REVISION A FEBRUARY 3, 2014
2
©2014 Integrated Device Technology, Inc.


Part Number ICS831721I
Description Differential Clock/Data Multiplexer
Maker IDT
Total Page 18 Pages
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