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ICS87002-05 Datasheet

1:2 LVCMOS/LVTTL-to-LVCMOS/LVTTL Zero Delay Buffer

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1:2 LVCMOS/LVTTL-to-LVCMOS/LVTTL
Zero Delay Buffer for Audio
ICS87002-05
General Description
ICS
HiPerClockS™
The ICS87002-05 is a 1:2 LVCMOS/LVTTL low phase
noise Zero Delay Buffer and is optimized for audio
frequencies.
The device uses third generation FemtoClock®
Technology for an optimum of high frequency and
excellent phase jitter performance, combined with a low power
consumption.
The device utilizes an internal feedback loop therefore eliminating
the complexity of an external feedback loop.
The device utilizes a 3.3V supply and is packaged in a small,
lead-free (RoHS 6) 8-lead SOIC package.
DATA SHEET
Features
Third generation FemtoClock® technology
Low phase noise zero delay buffer
Low skew outputs
One LVCMOS/LVTTL clock input
Two LVCMOS/LVTTL outputs
Phase noise: -125dBc/Hz @1kHz offset; -130dBc/Hz @100kHz
offset
Cycle-to-cycle jitter: 60ps (maximum)
0°C to 70°C ambient operating temperature
Full 3.3V supply voltage
Supported Input Reference Clock Frequencies
REF_CLK Frequencies
11.2896MHz
12.288MHz
16.384MHz
16.9344MHz
18.432MHz
22.5792MHz
24.576MHz
Block Diagram
REF_CLK
PFD
&
LPF
VCO
Internal feedback
Pin Assignment
REF_CLK 1
8 nc
VDD 2
7 Q1
Q1
GND 3
6 VDD
Q2 4
5 GND
Q2 ICS87002-05
8-lead SOIC
3.8mm x 4.8mm x 1.47mm
M Package
Top View
ICS87002BM-05 REVISION B APRIL 16, 2010
1
©2010 Integrated Device Technology, Inc.


Integrated Device Technology Electronic Components Datasheet

ICS87002-05 Datasheet

1:2 LVCMOS/LVTTL-to-LVCMOS/LVTTL Zero Delay Buffer

No Preview Available !

ICS87002-05 Data Sheet
1:2 LVCMOS/LVTTL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER FOR AUDIO
Table 1. Pin Descriptions
Number
1
2, 6
3, 5
4, 7
8
Name
REF_CLK
VDD
GND
Q2, Q1
nc
Type
Input
Power
Power
Output
Unused
Description
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Power supply pin.
Power supply ground.
Single-ended clock outputs. 15typical output impedance. LVCMOS/LVTTL interface level.
No connect.
Table 2. Pin Characteristics
Symbol
CIN
CPD
ROUT
Parameter
Input Capacitance
Power Dissipation Capacitance
Output Impedance
Test Conditions
VDD = 3.6V
VDD = 3.3V ± 0.3V
Minimum
Typical
4
8
15
Maximum
Units
pF
pF
ICS87002BM-05 REVISION B APRIL 16, 2010
2
©2010 Integrated Device Technology, Inc.


Part Number ICS87002-05
Description 1:2 LVCMOS/LVTTL-to-LVCMOS/LVTTL Zero Delay Buffer
Maker IDT
Total Page 12 Pages
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