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Integrated Device Technology Electronic Components Datasheet

ICS87008I Datasheet

1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

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ICS87008I
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS87008I is a low skew, 1:8 LVCMOS/LVTTL Clock
Generator. The device has 2 banks of 4 outputs and each
bank can be independently selected for ÷1 or ÷2 frequency
operation. Each bank also has its own power supply pins so
that the banks can operate at the following different voltage
levels: 3.3V, 2.5V, and 1.8V. The low impedance LVCMOS/
LVTTL outputs are designed to drive 50Ω series or parallel
terminated transmission lines.
The divide select inputs, DIV_SELA and DIV_SELB, control the
output frequency of each bank. The output banks can be
independently selected for ÷1 or ÷2 operation. The bank enable
inputs, CLK_ENA and CLK_ENB, support enabling and disabling
each bank of outputs individually. The CLK_ENA and CLK_ENB
circuitry has a synchronizer to prevent runt pulses when
enabling or disabling the clock outputs. The master reset
input, nMR/OE, resets the ÷1/÷2 flip flops and also controls the
active and high impedance states of all outputs. This pin has
an internal pull-up resistor and is normally used only for test
purposes or in systems which use low power modes.
The ICS87008I is characterized to operate with the core at 3.3V
or 2.5V and the banks at 3.3V, 2.5V, or 1.8V. Guaranteed bank,
output, and part-to-part skew characteristics make the 87008I
ideal for those clock applications demanding well-defined
performance and repeatability.
FEATURES
• Eight LVCMOS/LVTTL outputs (2 banks of 4 outputs)
• Selectable differential CLK1, nCLK1 or
LVCMOS clock input
CLK1, nCLK1 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• CLK0 supports the following input types:
LVCMOS, LVTTL
• Maximum output frequency: 250MHz
• Independent bank control for ÷1 or ÷2 operation
• Glitchless, asynchronous clock enable/disable
• Output skew: 105ps (maximum) @ 3.3V core/3.3V output
• Bank skew: 70ps (maximum) @ 3.3V core/3.3V output
• 3.3V or 2.5V core/3.3V, 2.5V, or 1.8V output operating
supply
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
nMR/OE
DIV_SELA
CLK1
nCLK1
CLK0
CLK_ENA
CLK_SEL
1
0
CLK_ENB
÷1 1
÷2 0
1
0
DIV_SELB
LE
D
LE
D
87008AGI
PIN ASSIGNMENT
4 QA0:QA3
4
QB0:QB3
CLK1
nCLK1
VDDOA
QA0
QA1
GND
QA2
QA3
VDDOA
DIV_SELA
CLK_ENA
VDD
1
2
3
4
5
6
7
8
9
10
11
12
24 CLK0
23 CLK_SEL
2 2 VDDOB
21 QB0
20 QB1
19 GND
18 QB2
17 QB3
1 6 VDDOB
15 DIV_SELB
14 CLK_ENB
13 nMR/OE
ICS87008I
24-Lead TSSOP
4.4mm x 7.8mm x 0.92mm body package
G Package
Top View
www.idt.com
1
REV. B JULY 31, 2010


Integrated Device Technology Electronic Components Datasheet

ICS87008I Datasheet

1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

No Preview Available !

ICS87008I
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
CLK1
Input Pulldown Non-inverting differential clock input.
2
nCLK1
Input
Pullup/
Pulldown
Inverting differential clock input. VDD/2 default when left floating.
3, 9
4, 5, 7, 8
VDDOA
QA0, QA1,
QA2, QA3
Power
Output
Output Bank A supply pins.
Bank A outputs. LVCMOS / LVTTL interface levels.
6, 19
GND
Power
Supply ground.
10
11
12
13
14
15
16, 22
17, 18, 20, 21
23
24
DIV_SELA
CLK_ENA
VDD
nMR/OE
CLK_ENB
DIV_SELB
VDDOB
QB3, QB2,
QB1, QB0
CLK_SEL
CLK0
Input
Input
Power
Input
Input
Input
Power
Output
Input
Input
Pullup
Pullup
Pullup
Pullup
Pullup
Controls frequency division for Bank A outputs.
LVCMOS / LVTTL interface levels.
Output enable for Bank A outputs. Active HIGH.
If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels.
Power supply pin.
Master reset. When LOW, resets the ÷1/÷2 flip flops and sets the
outputs to high impedance. LVCMOS / LVTTL interface levels.
Output enable for Bank B outputs. Active HIGH.
If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels.
Controls frequency division for Bank B outputs.
LVCMOS / LVTTL interface levels..
Output Bank B supply pins.
Bank B outputs. LVCMOS / LVTTL interface levels.
Pulldown
Clock select input. When HIGH, selects CLK1, nCLK1 inputs.
When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels.
Pulldown LVCMOS / LVTTL clock input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
CIN
RPULLUP
RPULLDOWN
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
CPD
Power Dissipation
Capacitance (per output)
ROUT
Output Impedance
NOTE 1: VDDOx denotes VDDOA and VDDOB.
VDD, VDDOx = 3.465V; NOTE 1
VDD, VDDOx = 2.625V; NOTE 1
VDD = 3.465, VDDOx = 2.625V; NOTE 1
V = 3.465, V = 1.89V; NOTE 1
DD DDOx
VDD = 2.625, VDDOx = 1.89V; NOTE 1
Minimum
Typical
4
51
51
7
Maximum
18
20
20
30
20
Units
pF
kΩ
kΩ
pF
pF
pF
pF
pF
Ω
TABLE 3. FUNCTION TABLE
nMR/OE
0
1
1
1
Inputs
CLK_ENx
X
1
1
0
DIV_SELx
X
0
1
X
Outputs
Bank X Qx Frequency
Hi Z N/A
Active
fIN/2
Active
fIN
Low N/A
87008AGI
www.idt.com
2
REV. B JULY 31, 2010


Part Number ICS87008I
Description 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
Maker IDT
Total Page 16 Pages
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