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* 2 - CPU differential low power push-pull pairs 10 - SRC differential low power push-pull pairs 1 - CPU/SRC selectable dif.

PIN # PIN NAME TYPE DESCRIPTION 3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before .

ICS9LPRS502

ICS9LPRS525

ICS9LPRS535

ICS9LPRS545

ICS9LPRS365

ICS9LPRS436C

ICS9LPRS462

ICS9LPRS464

ICS9LPRS480

ICS9LPR426A

ICS9LPR501

ICS9LP525-2

ICS9LRS3187B