IDT709149S Datasheet | IDT

.. HIGH-SPEED 36K (4K x 9-BIT) SYNCHRONOUS PIPELINED DUAL-PORT SRAM Features x x IDT709149S x x x Architecture based on Dual-Port SRAM cells – Allows full simultaneous access from both ports High-speed clock-to-data output times – mercial: 8/10/12ns (max.) Low-power operation – IDT709149S Active: 1500mW (typ.) Standby: 75mW (typ.) 4K X 9 bits Synchronous operation – 4ns setup to clock, 1ns hold on all control, data, and address inputs – Data input, address, and control registers – Fast 8ns clock to data out x x x x x 13ns cycle time, 76MHz operation in pipeline mode – Self-timed write allows for fast cycle times TTL-patible, singles 5V (±10%) power supply...