IDT70V631S Datasheet | IDT

Features - - - - - - - Fully asynchronous operation from either port Separate byte controls for multiplexed bus and bus matching patibility Supports JTAG features pliant to IEEE 1149.1 - Due to limited pin count, JTAG is not supported on the 128-pin TQFP package. LVTTL-patible, single 3.3V (±150m V) power supply for core LVTTL-patible, selectable 3.3V (±150m V)/2.5V (±100m V) power supply for I/Os and control signals on each port Available in a 128-pin Thin Quad Flatpack, 208-ball fine pitch Ball Grid Array, and 256-ball Ball Grid Array Industrial temperature range (- 40°C to +85°C) is available for selected speeds Functional Block Diagram UBL LBL UBR LBR R/ WL B E 0 L B E 1 L B E 1 R B E 0 R R/WR CE0L CE1L CE0 R CE1 R OEL Dout0-8_L Dout9-17_L Dout0-8_R Dout9-17_R 256K x 18 MEMORY ARRAY I/O0L- I/O17L Din_L Din_R I/O0R - I/O17R A17L A0L Address Decoder ADDR_L ADDR_R Address Decoder A17R A0R CE0L CE1L R/WL BUSYL SEML INTL ARBITRATION INTERRUPT SEMAPHORE LOGIC CE0 R CE1 R R/WR BUSYR M/ S SEM R INTR TDI TDO JTAG TMS TCK TRST 5622 drw 01 NOTES: 1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull). OCTOBER...