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IDT71V547XS - 3.3V Synchronous SRAM

Download the IDT71V547XS datasheet PDF. This datasheet also covers the IDT71V547S variant, as both devices belong to the same 3.3v synchronous sram family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • 128K x 36 memory configuration, flow-through outputs.
  • Supports high performance system speed - 95 MHz (8ns Clock-to-Data Access).
  • ZBTTM Feature - No dead cycles between write and read cycles.
  • Internally synchronized signal eliminates the need to control OE Functional Block Diagram LBO Address A [0:16] CE1, CE2, CE2 R/W CEN ADV/LD BWx DQ DQ.
  • Single R/W (READ/WRITE) control pin.
  • 4-word burst capability (Interleaved or linear).
  • Individual byte write (BW1 - BW4.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IDT71V547S-IDT.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number IDT71V547XS
Manufacturer IDT
File Size 696.98 KB
Description 3.3V Synchronous SRAM
Datasheet download datasheet IDT71V547XS Datasheet

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Other Datasheets by IDT

Part Number Description
IDT71V547S 3.3V Synchronous SRAM
IDT71V546S 3.3V Synchronous SRAM
IDT71V016 3.3V CMOS Static RAM
IDT71V124SA 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
128K X 36, 3.3V Synchronous IDT71V547S/XS SRAM with ZBT™ Feature, Burst Counter and Flow-Through Outputs Features ◆ 128K x 36 memory configuration, flow-through outputs ◆ Supports high performance system speed - 95 MHz (8ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized signal eliminates the need to control OE Functional Block Diagram LBO Address A [0:16] CE1, CE2, CE2 R/W CEN ADV/LD BWx DQ DQ ◆ Single R/W (READ/WRITE) control pin ◆ 4-word burst capability (Interleaved or linear) ◆ Individual byte write (BW1 - BW4) control (May tie active) ◆ Three chip enables for simple depth expansion ◆ Single 3.