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Integrated Device Technology Electronic Components Datasheet

IDT7200L Datasheet

CMOS ASYNCHRONOUS FIFO

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CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
IDT7200L
IDT7201LA
IDT7202LA
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
FEATURES:
First-In/First-Out dual-port memory
256 x 9 organization (IDT7200)
512 x 9 organization (IDT7201)
1,024 x 9 organization (IDT7202)
Low power consumption
— Active: 440mW (max.)
—Power-down: 28mW (max.)
Ultra high speed—12ns access time
Asynchronous and simultaneous read and write
Fully expandable by both word depth and/or bit width
720x family is pin and functionally compatible from 256 x 9 to 64k x 9
Status Flags: Empty, Half-Full, Full
Auto-retransmit capability
High-performance CEMOS™ technology
Military product compliant to MIL-STD-883, Class B
Standard Military Drawing #5962-87531, 5962-89666, 5962-89863
and 5962-89536 are listed on this function
Dual versions available in the TSSOP package. For more informa-
tion, see IDT7280/7281/7282 data sheet
IDT7280 = 2 x IDT7200
IDT7281 = 2 x IDT7201
IDT7282 = 2 x IDT7202
Industrial temperature range (–40oC to +85oC) is available
(plastic packages only)
Green parts available, see ordering information
DESCRIPTION:
The IDT7200/7201/7202 are dual-port memories that load and empty data
onafirst-in/first-outbasis. ThedevicesuseFullandEmptyflagstopreventdata
overflow and underflow and expansion logic to allow for unlimited expansion
capability in both word size and depth.
The reads and writes are internally sequential through the use of ring
pointers, with no address information required to load and unload data. Data
is toggled in and out of the devices through the use of the Write (W) and Read
(R) pins.
The devices utilize a 9-bit wide data array to allow for control and parity bits
at the user’s option. This feature is especially useful in data communications
applications where it is necessary to use a parity bit for transmission/reception
errorchecking. ItalsofeaturesaRetransmit(RT)capabilitythatallowsforreset
of the read pointer to its initial position when RT is pulsed LOW to allow for
retransmission from the beginning of data. A Half-Full Flag is available in the
single device mode and width expansion modes.
These FIFOs are fabricated using high-speed CMOS technology. They
are designed for those applications requiring asynchronous and simultaneous
read/writes in multiprocessing and rate buffer applications. Military grade
product is manufactured in compliance with MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
W
WRITE
CONTROL
DATA INPUTS
(D0-D8)
WRITE
POINTER
RAM
ARRAY
256 x 9
512 x 9
1,024 x 9
READ
POINTER
R
READ
CONTROL
THREE-
STATE
BUFFERS
DATA OUTPUTS
(Q0-Q8)
FLAG
LOGIC
EF
FF
RS
RESET
LOGIC
FL/RT
EXPANSION
XI
LOGIC
XO/HF
2679 drw 01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
COMMERCIAL, INDUSTRIAL AND MILITARY TEMPERATURE RANGES
1
©2017 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2017
DSC-2679/15


Integrated Device Technology Electronic Components Datasheet

IDT7200L Datasheet

CMOS ASYNCHRONOUS FIFO

No Preview Available !

IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURERANGES
PIN CONFIGURATIONS
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
Q3
Q8
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
D4
D5
D6
D7
FL/RT
RS
EF
XO/HF
Q7
Q6
Q5
Q4
R
2679 drw 02a
INDEX
D2
D1
D0
XI
FF
Q0
Q1
NC
Q2
4 3 2 1 32 31 30
5 29
6 28
7 27
8 26
9 25
10 24
11 23
12 22
13 21
14 15 16 17 18 19 20
D6
D7
NC
FL/RT
RS
EF
XO/HF
Q7
Q6
2679 drw 02b
Package Type
PLASTIC DIP(1)
PLASTIC THIN DIP
CERDIP(1)
THIN CERDIP
SOIC
Reference
Identifier
P28-1
P28-2
D28-1
D28-3
SO28-3
Order
Code
P
TP
D
TD
SO
TOP VIEW
NOTE:
1. The 600-mil-wide DIP (P28-1 and D28-1) and LCC are not available for the IDT7200.
Package Type
LCC(1)
PLCC
Reference
Identifier
L32- 1
J32-1
TOP VIEW
Order
Code
L
J
ABSOLUTE MAXIMUM RATINGS
Symbol
Rating
Com’l & Ind'l
Mil. Unit
VTERM
Terminal Voltage
with Respect
to GND
–0.5 to +7.0
–0.5 to +7.0 V
TSTG Storage
Temperature
–55 to +125
–65 to +155 °C
IOUT DC Output
Current
–50 to +50
–50 to +50 mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Parameter
Min. Typ. Max.
VCC Supply Voltage
Commercial/Industrial/Military
4.5 5.0 5.5
GND Supply Voltage
00
0
VIH(1) Input High Voltage Com'l/Ind'l
VIH(1) Input High Voltage Military
VIL(2) Input Low Voltage
Commercial/Industrial/Military
2.0 —
2.2 —
——
0.8
TA OperatingTemperatureCommercial 0 — 70
TA OperatingTemperatureIndustrial
TA OperatingTemperatureMilitary
–40 —
–55 —
85
125
Unit
V
V
V
V
V
°C
°C
°C
NOTES:
1. For RT/RS/XI input, VIH = 2.6V (commercial).
For RT/RS/XI input, VIH = 2.8V (military).
2. 1.5V undershoots are allowed for 10ns once per cycle.
2


Part Number IDT7200L
Description CMOS ASYNCHRONOUS FIFO
Maker IDT
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IDT7200L Datasheet PDF






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