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IDT74AHCT373 Datasheet

High Speed CMOS Octal Transparent Latch

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FEATURES:
• Equivalent to ALS speeds and output drive over full
temperature and voltage supply extremes
• 10ns typical data to output delay
• IOL = 14mA over full military temperature range
• CMOS power levels (5p.W typo static)
• Both CMOS and TTL output compatible
• Substantially lower input current levels than ALS (5p.A max.)
• Octal transparent latch with enable
• 100% product assurance screening to MIL-STD-883, Class B
is available
• JEDEC standard pinout for DIP and LCC
DESCRIPTION:
The IDT54/74AHCT373 are 8-bit latches built using advanced
CEMOS'", a dual metal CMOS technology. This octal latch has
3-state output and is intended for bus-oriented applications. The
flip-flops appear transparent to the data when Latch Enable (LE)
is HIGH. When LE is LOW, the data that meets the setup times is
latched. Data appears on the bus when the Output Enable (OE)
is LOW. When bE is HIGH, the bus output is in the high
impedance state.
PIN CONFIGURATIONS
De
00
Do
0,
0,
0,
0,
0,
0,
GND
v"
0,
0,
0,
0,
0,
0,
D.
O.
lE
SSD54174AHCT373-001
DIP
TOPYIEW
FUNCTIONAL BLOCK DIAGRAM
DO 0,
0,
0,
03 D2 020, D1
0,
GND
LE
0,
0,
LJ LJ LJ LJLJ
::::9 8 7 6 5 43::::
::10 2:::
::11 1~::
::12 20::::
I.~13
~
15 16 17 1~9::
nr1n r1 r1
Do
00
De
v"
0,
05 Os 0& 08 07
SSOS4174AHCT373-002
LCC
TOPYIEW
0, 0, 07
LE --~~~--~----+---~~---4----~----~----~----~---4~---+----~----+---~~---4----~
De --~~----~----+---~~---4----~----~----~----~---4~---+----~----+---~~---4----~
00 0, 0, 0,
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
@1986 Integrated Device Technology, rnc.
5-61
0, o. 0,
SSD54174AHCT373-003
JULY 1986
Printed in U.S.A.


Integrated Device Technology Electronic Components Datasheet

IDT74AHCT373 Datasheet

High Speed CMOS Octal Transparent Latch

No Preview Available !

IDT54/74AHCT373 HIGH-SPEED CMOS OCTAL TRANSPARENT LATCH
ABSOLUTE MAXIMUM RATING(l)
SYMBOL
RATING
COMMERCIAL MILITARY UNIT
VTERM
Terminal Voltage
with Respect
toGND
-0.5 to +7.0 -0.5 to +7.0 V
TA
Operating
Temperature
oto +70
-55 to +125 ·C
TelAs
Temperature
Under Bias
-55 to +125 -65 to +135 ·C
TSTG
Storage
Temperature
-55 to +125 -65 to +155 ·C
lOUT DC Output Current
120
120 mA
NOTE:
1.Stressesgreaterthanthose listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = O°C to +70°C
Vee = 5.0V ± 5%
Min. = 4.75V
Max. = 5.25V (Commercial)
TA = -55°C to +125°C
Vee = 5.0V ± 10%
Min. = 4.50V
Max. = 5.50V (Military)
VLe = 0.2V
VHe = Vee - 0.2V
SYMBOL
V,H
V,L
I'H
I,L
PARAMETER
Input HIGH Level
Input LOW Level
Input HIGH Current
Input LOW Current
TEST CONDITIONS(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
Vce = Max., Y,N = Vec
Vcc = Max., Y'N = GND
MIN. TYp'I')
2.0 -
--
--
--
Ise Short Circuit Current
Vce = Max. (3)
-60 -100
Vee = 3V, Y'N = VLe or VHe, 10H = -321'A
VHC Vee
VOH Output HIGH Voltage
Vec= Min.
Y,N = V,H or V,L
10H = -150p.A
10H = -1.0mA MIL
10H = -2.6mA COM
VHe
2.4
2.4
Vee
4.3
4.3
VOL Output LOW Voltage
Vec = 3V, Y,N = VLe or VHe, 10L = 300pA
Vee = Min.
Y,N = V,H or V,L
10L = 300p.A
10L = 14mA MIL
10L = 24mA COM
- GND
- GND
--
--
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V. +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
MAX.
-
0.8
5
-5
-
-
-
-
-
VLe
VLC
0.4
0.5
UNIT
V
V
pA
p.A
mA
V
V
5-62


Part Number IDT74AHCT373
Description High Speed CMOS Octal Transparent Latch
Maker IDT
Total Page 4 Pages
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