FEATURES:
• Equivalent to ALS speeds and output drive over full
temperature and voltage supply extremes
• 10ns typical address to output delay
• IOL = 14mA over full military temperature range
• CMOS power levels (5p.W typo static)
• Both CMOS and TTL output compatible
• Substantially lower input current levels than ALS (5p.A max.)
• Octal D register (3-state)
• 100% product assurance screening to MIL-STD-833, Class B
is available
• JEDEC standard pinout for DIP and LCC
DESCRIPTION:
The IDT54/74AHCT374 are 8-bit registers built using advanced
CEMOS'", a dual metal CMOS technology. This register consists
of eight D-type flip-flops with a buffered common clock and
bu~ered three-state output control. When the output enable (OE)
inp~t is LOW, the eight outputs are enabled. When the OE input is
HIGH, the outputs are in the three-state conditions.
Input data meeting the set-up and hold time requirements of
the D inputs is transferred to the 0 outputs on the LOW-to-HIGH
transition of the clock input.
PIN CONFIGURATIONS
OE
00
00
01
01
02
02
03
03
GNO
Vee
07
07
06
06
Os
Os
04
04
CP
SSD54!74AHCT374~()()1
OIP
TOP VIEW
FUNCTIONAL BLOCK DIAGRAM
CP
CLOCK
00
88~~o
Ul J LJ I ILJ l J
01 ~43 2
20 1918 ::: 07
01 :::5
1 17~ 06
02 :::6
16~ 06
02 :::7
1S::: OS
03 Os
SSD54174AHCT374-002
LCC
TOP VIEW
Os 06
OE
OUTPUT~I~~~~--~~~----~+-----+-+-----~~----~-+----~~----~
ENABLE
00 Os 06
07
SSOS4/74AHCT374-0D3
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
@19861ntegrated Device Technology, Inc.
5-65
JULY 1986
Printed in the U.S.A.
