IDT74SSTU32D869 buffer equivalent, 14-bit 1:2 registered buffer.
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1.8V Operation Designed to drive low impedance nets SSTL_18 style clock and data inputs Differential CLK input Control i.
* Along with CSPU877/A/D DDR2 PLL, provides complete solution for DDR2 DIMMs
* Optimized for DDR2-400/533 [PC2.
This device supports low-power standby operation. When the reset input (RESET) is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is l.
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