Datasheet Details
| Part number | IDT74SSTUBH32865A |
|---|---|
| Manufacturer | IDT |
| File Size | 446.43 KB |
| Description | 28-BIT 1:2 REGISTERED BUFFER |
| Datasheet | IDT74SSTUBH32865A_IDT.pdf |
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Overview: www.DataSheet4U.com DATASHEET 28-BIT 1:2 REGISTERED BUFFER FOR DDR2 IDT74SSTUBH32865A The IDT74SSTUBH32865A includes a parity checking function. The IDT74SSTUBH32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain PTYERR pin (active LOW).
| Part number | IDT74SSTUBH32865A |
|---|---|
| Manufacturer | IDT |
| File Size | 446.43 KB |
| Description | 28-BIT 1:2 REGISTERED BUFFER |
| Datasheet | IDT74SSTUBH32865A_IDT.pdf |
|
|
|
This 28-bit 1:2 registered buffer with parity is designed for 1.7V to 1.9V VDD operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18.
The control inputs are LVCMOS.
Compare IDT74SSTUBH32865A distributor prices and check real-time stock availability from major suppliers. Prices and inventory may vary by region and order quantity.
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