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IDT74SSTUBF32868A Datasheet - IDT

28-BIT CONFIGURABLE REGISTERED BUFFER

IDT74SSTUBF32868A Features

* 28-bit 1:2 registered buffer with parity check functionality

* Supports SSTL_18 JEDEC specification on data inputs and outputs Applications

* DDR2 Memory Modules

* Provides complete DDR DIMM solution with ICS98ULPA877A or IDTCSPUA877A

* Supports LVCMOS swi

IDT74SSTUBF32868A General Description

This 28-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation. All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All outputs are edge-controlled circuits opti.

IDT74SSTUBF32868A Datasheet (568.97 KB)

Preview of IDT74SSTUBF32868A PDF

Datasheet Details

Part number:

IDT74SSTUBF32868A

Manufacturer:

IDT

File Size:

568.97 KB

Description:

28-bit configurable registered buffer.
www.DataSheet4U.com DATASHEET 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 IDT74SSTUBF32868A occurred on the open-drain QERR pin (active low). Th.

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IDT74SSTUBF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER IDT

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