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IDT74SSTUBF32865A - 28-BIT 1:2 REGISTERED BUFFER

Datasheet Summary

Description

This 28-bit 1:2 registered buffer with parity is designed for 1.7V to 1.9V VDD operation.

All clock and data inputs are compatible with the JEDEC standard for SSTL_18.

The control inputs are LVCMOS.

Features

  • 28-bit 1:2 registered buffer with parity check functionality.
  • Supports SSTL_18 JEDEC specification on data inputs.
  • and outputs Supports LVCMOS switching levels on CSGateEN and RESET inputs Low voltage operation: VDD = 1.7V to 1.9V Available in 160-ball LFBGA package.

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Datasheet Details

Part number IDT74SSTUBF32865A
Manufacturer IDT
File Size 295.52 KB
Description 28-BIT 1:2 REGISTERED BUFFER
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www.DataSheet4U.com DATASHEET 28-BIT 1:2 REGISTERED BUFFER WITH PARITY IDT74SSTUBF32865A The IDT74SSTUBF32865A includes a parity checking function. The IDT74SSTUBF32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain PTYERR pin (active LOW). Description This 28-bit 1:2 registered buffer with parity is designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The IDT74SSTUBF32865A operates from a differential clock (CLK and CLK).
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