IDT74SSTUBH32865A Description
This 28-bit 1:2 registered buffer with parity is designed for 1.7V to 1.9V VDD operation. All clock and data inputs are patible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS.
IDT74SSTUBH32865A Key Features
- Double Drive strength for heavily-loaded DIMM
IDT74SSTUBH32865A Applications
- 28-bit 1:2 registered buffer with parity check functionality
- Supports SSTL_18 JEDEC specification on data inputs