Datasheet4U Logo Datasheet4U.com

IDT74SSTUBH32868A - 28-BIT CONFIGURABLE REGISTERED BUFFER

Datasheet Summary

Description

This 28-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation.

All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS.

Features

  • 28-bit 1:2 registered buffer with parity check functionality.
  • Supports SSTL_18 JEDEC specification on data inputs and outputs.

📥 Download Datasheet

Datasheet preview – IDT74SSTUBH32868A

Datasheet Details

Part number IDT74SSTUBH32868A
Manufacturer IDT
File Size 552.43 KB
Description 28-BIT CONFIGURABLE REGISTERED BUFFER
Datasheet download datasheet IDT74SSTUBH32868A Datasheet
Additional preview pages of the IDT74SSTUBH32868A datasheet.

📁 Similar Datasheet

Other Datasheets by IDT

Full PDF Text Transcription

Click to expand full text
www.DataSheet4U.com DATASHEET 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 IDT74SSTUBH32868A occurred on the open-drain QERR pin (active low). The convention is even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. To calculate parity, all DIMM-independent D-inputs must be tied to a known logic state. If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or until RESET is driven low. If two or more consecutive parity errors occur, the QERR output is driven low and latched low for a clock duration equal to the parity error duration or until RESET is driven low.
Published: |