IDTCSP2510D driver equivalent, 3.3v phase-lock loop clock driver.
DESCRIPTION:
* Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
* Distributes one clock input to one bank of ten outputs
* Output enable .
* Distributes one clock input to one bank of ten outputs
* Output enable bank control
* External feedback (F.
* Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
* Distributes one clock input to one bank of ten outputs
* Output enable bank control
* External feedback (FBIN) pin is used to synchronize the outputs to the clo.
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