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IDTCSP2510D - 3.3V PHASE-LOCK LOOP CLOCK DRIVER

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Part number IDTCSP2510D
Manufacturer IDT
File Size 91.80 KB
Description 3.3V PHASE-LOCK LOOP CLOCK DRIVER
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Description

Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes one clock input to one bank of ten outputs Output enable bank control External feedback (FBIN) pin is used to synchronize the outputs to the clock input signal No external RC network required for PLL loop stability Operates at 3.3V VDD tpd Phase Error at 166MHz: < ±150ps Jitter (peak-to-peak) at 166MHz: < ±75ps @ 166MHz Spread

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