Datasheet Details
| Part number | IDTCSP2510D |
|---|---|
| Manufacturer | IDT |
| File Size | 91.80 KB |
| Description | 3.3V PHASE-LOCK LOOP CLOCK DRIVER |
| Download | IDTCSP2510D Download (PDF) |
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| Part number | IDTCSP2510D |
|---|---|
| Manufacturer | IDT |
| File Size | 91.80 KB |
| Description | 3.3V PHASE-LOCK LOOP CLOCK DRIVER |
| Download | IDTCSP2510D Download (PDF) |
|
|
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: • Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications • Distributes one clock input to one bank of ten outputs • Output enable bank control • External feedback (FBIN) pin is used to synchronize the outputs to the clock input signal • No external RC network required for PLL loop stability • Operates at 3.3V VDD • tpd Phase Error at 166MHz: < ±150ps • Jitter (peak-to-peak) at 166MHz: < ±75ps @ 166MHz • Spread Spectrum Compatible • Operating frequency 50MHz to 175MHz • Available in 24-Pin TSSOP package IDTCSP2510D APPLICATIONS: • SDRAM Modules • PC Motherboards • Workstations The CSP2510D is a high performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver.
It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
It is specifically designed for use with synchronous DRAMs.
www.DataSheet4U.com IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER 0°C TO 85°C TEMPERATURE RANGE 3.
| Brand Logo | Part Number | Description | Manufacturer |
|---|---|---|---|
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