IDTCSP2510C - 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER

Datasheet Summary

Description

c 1999 Integrated Device Technology, Inc.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

Features

Phase-Lock Loop Clock Distribution for Synchronous DRAM.

Integrated Device

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Datasheet Details

Part number	IDTCSP2510C
Manufacturer	Integrated Device
File Size	63.40 KB
Description	3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
Datasheet	IDTCSP2510C Datasheet
Additional preview pages of the IDTCSP2510C datasheet.

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Full PDF Text Transcription

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IDTCSP2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER 0ºC TO 85ºC TEMPERATURE RANGE 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER FEATURES: • Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications • Distributes one clock input to one bank of ten outputs • Output enable bank control • External feedback (FBIN) pin is used to synchronize the outputs to the clock input signal • No external RC network required for PLL loop stability • Operates at 3.

Published: Apr 17, 2005 |