IDTCSP2510D - 3.3V PHASE-LOCK LOOP CLOCK DRIVER

Datasheet Summary

Description

Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes one clock input to one bank of ten outputs Output enable bank control External feedback (FBIN) pin is used to synchronize the outputs to the clock input signal No exter

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IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER by IDT - Datasheet Preview — Datasheet preview – IDTCSP2510D

Datasheet Details

Part number	IDTCSP2510D
Manufacturer	IDT
File Size	91.80 KB
Description	3.3V PHASE-LOCK LOOP CLOCK DRIVER
Datasheet	IDTCSP2510D Datasheet
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www.DataSheet4U.com IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER 0°C TO 85°C TEMPERATURE RANGE 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER FEATURES: DESCRIPTION: • Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications • Distributes one clock input to one bank of ten outputs • Output enable bank control • External feedback (FBIN) pin is used to synchronize the outputs to the clock input signal • No external RC network required for PLL loop stability • Operates at 3.

Published: Feb 27, 2007 |