IDTCSP2510D Description
Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes one clock input to one bank of ten outputs Output enable bank control External feedback (FBIN) pin is used to synchronize the outputs to the clock input signal No external RC network required for PLL loop stability Operates at 3.3V VDD tpd Phase Error at 166MHz: < ±150ps Jitter (peak-to-peak) at 166MHz: < ±75ps @ 166MHz Spread Spectrum...
IDTCSP2510D Key Features
- Phase-Lock Loop Clock Distribution for Synchronous DRAM
IDTCSP2510D Applications
- Distributes one clock input to one bank of ten outputs