Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
Distributes one clock input to one bank of ten outputs
Output enable bank control
External feedback (FBIN) pin is used to synchronize the outputs to the clock input signal
No exter
Full PDF Text Transcription for IDTCSP2510D (Reference)
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IDTCSP2510D. For precise diagrams, and layout, please refer to the original PDF.
www.DataSheet4U.com IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER 0°C TO 85°C TEMPERATURE RANGE 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER FEATURES: DESCRIPTION:...
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PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER FEATURES: DESCRIPTION: • Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications • Distributes one clock input to one bank of ten outputs • Output enable bank control • External feedback (FBIN) pin is used to synchronize the outputs to the clock input signal • No external RC network required for PLL loop stability • Operates at 3.
IDTCSP2510D Datasheet
