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IN74AC112 Dual J-K Negative-Edge-Triggered Flip-Flop

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Description

TECHNICAL DATA IN74AC112 Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The IN74AC112 is identical in pinout to the LS/ALS112, H.

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Datasheet Specifications

Part number
IN74AC112
Manufacturer
IK Semiconductor
File Size
316.53 KB
Datasheet
IN74AC112_IKSemiconductor.pdf
Description
Dual J-K Negative-Edge-Triggered Flip-Flop

Applications

* of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e. g. , either GND or VCC). Unused outputs must be lef

IN74AC112 Distributors

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Dual J-K Negative-Edge-Triggered Flip-Flop IK Semiconductor
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