IS42S83200C Overview
Description
IS42S83200C is organized as 4-bank x 8,388,608-word x 8-bit Synchronous DRAM with LVTTL interface and IS42S16160C is organized as 4-bank x 4,194,304-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK.
Key Features
- Single 3.3V ±0.3V power supply
- Max. Clock frequency
- 6:166MHz<3-3-3>/-7:143MHz<3-3-3>/-75:133MHz<3-3-3>
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
