IS42VM16800E Datasheet | ISSI

FEATURES - Fully synchronous; all signals referenced to a positive clock edge - Internal bank for hiding row access and pre- charge - Programmable CAS latency: 2, 3 - Programmable Burst Length: 1, 2, 4, 8, and Full Page - Programmable Burst Sequence: - Sequential and Interleave - Auto Refresh (CBR) - TCSR (Temperature pensated Self Refresh) - PASR (Partial Arrays Self Refresh): 1/16, 1/8, 1/4, 1/2, and Full - Deep Power Down Mode (DPD) - Driver Strength Control (DS): 1/4, 1/2, and Full OPTIONS - Configurations: 16M x 8, 8M x 16, 4M x 32 - Power Supply IS42VMxxx - Vdd/Vddq = 1.8 V - Packages: x8 / x16 - TSOP II (54), BGA (54) [x16 only] x32 - TSOP II (86), BGA (90) - Temperature Range: mercial (0°C to +70°C) Industrial (- 40 ºC to 85 ºC) Automotive, A1 (- 40 ºC to 85 ºC) Automotive, A2 (- 40 ºC to 105 ºC) JUNE 2011 DESCRIPTION ISSI's 128Mb Mobile Synchronous DRAM achieves highspeed data transfer using pipeline architecture. All input and output signals refer to the rising edge of the clock input. Both write and read accesses to the SDRAM are burst oriented. The 128Mb Mobile Synchronous DRAM is designed to minimize current consumption making it ideal for low-power applications. Both TSOP and BGA packages are offered, including industrial grade products. KEY TIMING PARAMETERS Parameter CLK Cycle Time CAS Latency = 3 CAS Latency = 2 CLK Frequency CAS Latency = 3 CAS Latency = 2 Access Time from CLK CAS Latency = 3 CAS Latency = 2 -75 7.5 9.6 133 104 5.4 8.0 -10 Unit 10 ns 12 ns 100 Mhz 83 Mhz 8.0 ns 9.0 ns ADDRESSING TABLE Parameter Configuration Refresh Count Row Addressing Column Addressing Bank Addressing Precharge Addressing 16M x...