IS42VS16160J Datasheet, ISSI

* Fully synchronous; all signals referenced to a positive clock edge
* Internal bank for hiding row access and pre- charge
* Programmable CAS latency: 2, 3.

ISSI's 256Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All input and output signals refer to the rising edge of the clock input. Both write and read accesses to the SDRAM are burst oriented. The 256Mb Synchronous.