IS61DDB22M36C Datasheet | ISSI

IS61DDB24M18C IS61DDB22M36C 4Mx18, 2Mx36 72Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM APRIL 2018 Features - 2Mx36 and 4Mx18 configuration available. - mon I/O read and write ports. - Max. 400 MHz clock for high bandwidth - Synchronous pipeline read with self-timed late write operation. - Double Data Rate (DDR) interface for read and write input ports. - Fixed 2-bit burst for read and write operations. - Clock stop support. - Two input clocks (K and K#) for address and control registering at rising edges only. - Two input clocks (C and C#) for data output control. - Two echo clocks (CQ and CQ#) that are delivered simultaneously with data. - +1.8V core power supply and 1.5V to 1.8V VDDQ,...