IS61DDB22M36 - DDR-II (Burst of 2) CIO Synchronous SRAMs

This page provides the datasheet information for the IS61DDB22M36, a member of the IS61DDB24M18 DDR-II (Burst of 2) CIO Synchronous SRAMs family.

Product Overview

Integrated Silicon Solution

Part number	IS61DDB22M36
Manufacturer	Integrated Silicon Solution
File Size	572.80 KB
Description	DDR-II (Burst of 2) CIO Synchronous SRAMs
Datasheet	IS61DDB22M36 Datasheet
Additional preview pages of the IS61DDB22M36 datasheet.

The 72Mb IS61DDB22M36 and IS61DDB24M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have a common I/O bus.

The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.

2M x 36 or 4M x 18.
On-chip delay-locked loop (DLL) for wide data valid window.
Common data input/output bus.
Synchronous pipeline read with self-timed late write operation.
Double data rate (DDR-II) interface for read and write input ports.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K) for address and control registering at rising edges only.
Two input cloc.

Other Datasheets by Integrated Silicon Solution

Published: Jul 25, 2016 |