Description
The 72Mb IS61DDB22M36C and IS61DDB24M18C are synchronous, high-performance CMOS static random access memory (SRAM) devices.
These SRAMs have a common I/O bus.
The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.
Features
- 2Mx36 and 4Mx18 configuration available.
- Common I/O read and write ports.
- Max. 400 MHz clock for high bandwidth.
- Synchronous pipeline read with self-timed late write
operation.
- Double Data Rate (DDR) interface for read and
write input ports.
- Fixed 2-bit burst for read and write operations.
- Clock stop support.
- Two input clocks (K and K#) for address and control
registering at rising edges only.
- Two input clocks (C and C#) for data output contro.
IS61DDB22M36C Datasheet
