Datasheet4U Logo Datasheet4U.com

IS61DDP2B41M18C1 - 18Mb DDR-IIP CIO SYNCHRONOUS SRAM

Download the IS61DDP2B41M18C1 datasheet PDF. This datasheet also covers the IS61DDP2B41M18C variant, as both devices belong to the same 18mb ddr-iip cio synchronous sram family and are provided as variant models within a single manufacturer datasheet.

Description

512Kx36 and 1Mx18 configuration available.

On-chip Delay-Locked Loop (DLL) for wide data valid window.

Common I/O read and write ports.

Synchronous pipeline read with self-timed late write operation.

Double Data Rate (DDR) interface for read and write input ports.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61DDP2B41M18C-ISSI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
IS61DDP2B41M18A 18Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM Integrated Silicon Solution
IS61DDP2B41M18A1 18Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM Integrated Silicon Solution
IS61DDP2B41M18A2 18Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM Integrated Silicon Solution
IS61DDP2B41M36A 36Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM Integrated Silicon Solution
IS61DDP2B41M36A1 36Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM Integrated Silicon Solution

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61DDP2B41M18C 18Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDP2B41M18C2 18Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDP2B451236C 18Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDP2B451236C1 18Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDP2B451236C2 18Mb DDR-IIP CIO SYNCHRONOUS SRAM

Full PDF Text Transcription

Click to expand full text
IS61DDP2B41M18C/C1/C2 IS61DDP2B451236C/C1/C2 1Mx18, 512Kx36 18Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM (2.0 Cycle Read Latency) APRIL 2016 FEATURES DESCRIPTION  512Kx36 and 1Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Common I/O read and write ports.  Synchronous pipeline read with self-timed late write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.0 cycle read latency.  Fixed 4-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  +1.8V core power supply and 1.5V to 1.8V VDDQ, used with 0.75 to 0.9V VREF.
Published: |