IS61NLP51218B
FEATURES
- 100 percent bus utilization
- No wait cycles between Read and Write
- Internal self-timed write cycle
- Individual Byte Write Control
- Single R/W (Read/Write) control pin
- Clock controlled, registered address, data and control
- Interleaved or linear burst sequence control us- ing MODE input
- Three chip enables for simple depth expansion and address pipelining
- Power Down mode
- mon data inputs and data outputs
- CKE pin to enable clock and suspend operation
- JEDEC 100-pin QFP, 165-ball BGA and 119-ball
BGA packages
- Power supply:
NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%) NVP: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NVVP: Vdd 1.8V (± 5%), Vddq 1.8V (± 5%)
- JTAG Boundary Scan for BGA packages
- Industrial temperature available
- Lead-free available
DESCRIPTION
The 9 Meg product family features high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and munications applications. They are...
