IS61NLP51218B Datasheet | ISSI

IS61NLP25636B/IS61NVP/NVVP25636B IS61NLP51218B/IS61NVP/NVVP51218B  ® Long-term Support World Class Quality 256K x 36 and 512K x 18 9Mb, PIPELINE 'NO WAIT' STATE BUS SRAM AUGUST 2019 Features - 100 percent bus utilization - No wait cycles between Read and Write - Internal self-timed write cycle - Individual Byte Write Control - Single R/W (Read/Write) control pin - Clock controlled, registered address, data and control - Interleaved or linear burst sequence control us- ing MODE input - Three chip enables for simple depth expansion and address pipelining - Power Down mode - mon data inputs and data outputs - CKE pin to enable clock and suspend operation - JEDEC 100-pin QFP, 165-ball BGA and 119-ball BGA packages - Power supply: NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%) NVP: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NVVP: Vdd 1.8V (± 5%), Vddq 1.8V (± 5%) - JTAG Boundary Scan for BGA packages - Industrial temperature available - Lead-free available DESCRIPTION The 9 Meg product family Features high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and munications applications. They are organized as 256K words by 36 bits and 512K words by 18 bits, fabricated with ISSI's advanced CMOS technology. Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal...