Title | (Alt: IS61QDB44M18C-333B4LI) |
Description | APRIL 2018 2Mx36 and 4Mx18 configuration available. Separate independent read and write ports with concurrent read and write operations. Max. 400 MHz clock for high bandwidth Synchronous pipeline read with late write operation. Double Data Rate (DDR) interface for read and write input ports. 1.5 cycle read latency. Fixed 4-bit burst for read and write operations. Clock stop suppo... |
Features |
DESCRIPTION
APRIL 2018
2Mx36 and 4Mx18 configuration available. Separate independent read and write ports with concurrent read and write operations. Max. 400 MHz clock for high bandwidth Synchronous pipeline read with late write operation. Double Data Rate (DDR) interface for read and write input ports. 1.5 cycle read latency. Fixe... |
Datasheet |
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Distributor |
![]() Avnet Silica |
Stock | 0 In stock |
Price |
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Distributor | Stock | Price | BuyNow |
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![]() Avnet Silica |
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