IS61VPS102436B Datasheet | ISSI

IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B 1M x 36, 1M x 32, 2M x 18 36 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM NOVEMBER 2017 Features - Internal self-timed write cycle - Individual Byte Write Control and Global Write - Clock controlled, registered address, data and control - Burst sequence control using MODE input - Three chip enable option for simple depth ex- pansion and address pipelining - mon data inputs and data outputs - Auto Power-down during deselect - Single cycle deselect - Snooze MODE for reduced-power standby - JTAG Boundary Scan for BGA package - Power Supply LPS: Vdd 3.3V (+ 5%), Vddq 3.3V/2.5V (+ 5%) VPS: Vdd 2.5V (+ 5%), Vddq 2.5V (+ 5%) VVPS: Vdd 1.8V (+ 5%), Vddq 1.8V (+ 5%) - JEDEC 100-Pin QFP, 119-ball BGA, and 165ball BGA packages - Lead-free available FAST ACCESS TIME Symbol tkq tkc Parameter Clock Access Time Cycle Time Frequency DESCRIPTION The 36Mb product family Features   high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for munication and networking applications. The IS61LPS/VPS102436B and IS64LPS102436B are organized as 1,048,476 words by 36 bits. The IS61LPS102432B is organized as 1,048,476 words by 32 bits.The IS61LPS/VPS204818B is organized as 2,096,952 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and highdrive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. The byte write operation is performed by using the byte write enable (BWE) input...