128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED,
SINGLE CYCLE DESELECT SRAM
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and
Burst sequence control using MODE input
Three chip enable option for simple depth
expansion and address pipelining
Common data inputs and data outputs
Auto Power-down during deselect
Single cycle deselect
Snooze MODE for reduced-power standby
JEDEC 100-pin QFP, 165-ball BGA and 119-
ball BGA packages
LPS: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)
VPS: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%)
JTAG Boundary Scan for BGA packages
Industrial and Automotive temperature support
Error Detection and Error Correction
FAST ACCESS TIME
Clock Access Time
The 4Mb product family features high-speed, low-power
synchronous static RAMs designed to provide burstable,
high-performance memory for communication and
networking applications. The IS61(64)LPS/VPS12836EC are
organized as 131,072 words by 36bits. The
IS61(64)LPS/VPS12832EC are organized as 131,072 words by
32bits. The IS61(64)LPS/VPS25618EC are organized as
262,144 words by 18 bits. Fabricated with ISSI's advanced
CMOS technology, the device integrates a 2-bit burst
counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous
inputs pass through registers controlled by a positive-
edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte
write enable (/BWE) input combined with one or more
individual byte write signals (/BWx). In addition, Global
Write (/GW) is available for writing all bytes at one time,
regardless of the byte write controls.
Bursts can be initiated with either /ADSP (Address Status
Processor) or /ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the /ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order.
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
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without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
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