* Pin-selectable PLL divider ratios support forward and inverse FEC ratio translation, including:
* 255/238 (OTU1) Mapping and 238/255 De-mapping
* 255/237 (OTU2) Mapping and 237/255 De-mapping
* 255/236 (OTU3) Mapping and 236/255 De-mapping Example I/O Clock Frequen
M2006-02
Integrated Circuit Solution Inc
83.76 KB
Vcso based fec clock pll / hitless switching option.
Integrated Circuit Systems, Inc. Product Brief M2006-02/-12 VCSO BASED FEC CLOCK PLL / HITLESS SWITCHING OPTION PIN ASSIGNMENT (9 x 9 mm SMT) FIN_S.
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