* Fully integrated PLL
* 5 differential HSTL outputs
* Selectable differential CLKx, nCLKx input pairs
* CLKx, nCLKx pairs can accept the following differ.

ICS BLOCK DIAGRAM Q0 nQ0 PLL_SEL ÷4, ÷8 0 1 1 PIN ASSIGNMENT PLL_SEL GND GND VDDO VDDA nQ4 VDD Q4 Q1 nQ1 0 CLK0 .

The ICS8624 is a high performance, 1-to-5 Differential-to-HSTL zero delay buffer and HiPerClockS™ a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8624 has two selectable clock input pairs. The CLK0, nCLK0 and .

ICS8602

ICS8633-01

ICS86953I-147

ICS810001-21

ICS81006

ICS81006I

ICS810251I

ICS813001I

ICS82C404

ICS8302

ICS8302-01

ICS83021I

ICS83023