ICS9248-135 Datasheet PDF - Integrated Circuit Systems Frequency Generator & Integrated Buffers Specs

ICS9248-135 - Frequency Generator & Integrated Buffers

Datasheet Summary

Description

The ICS9248-135 is the single chip clock solution for Desktop/Notebook designs using the SIS 540/630 style chipset.

It provides all necessary clock signals for such a system.

Spread spectrum may be enabled through I2C programming.

Features

3- CPUs @ 2.5/3.3V, up to 166MHz.
10 - SDRAM @ 3.3V, up to 166MHz including 2 SDRAM_F's.
7- PCI @3.3V,.
1- 48MHz, @3.3V fixed.
1- 24/48MHz, @3.3V selectable by I2C (Default is 24MHz).
2- REF @3.3V, 14.318MHz. Features:.
Up to 166MHz frequency support.
Support FS0-FS3 trapping status bit for I2C read back.
Support power management: CPU, PCI, SDRAM stop and Power down Mode form I2C programming.
Spread.

Datasheet Details

Part number	ICS9248-135
Manufacturer	Integrated Circuit Systems
File Size	191.67 KB
Description	Frequency Generator & Integrated Buffers
Datasheet	ICS9248-135 Datasheet
Additional preview pages of the ICS9248-135 datasheet.

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Full PDF Text Transcription

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Integrated Circuit Systems, Inc. ICS9248-135 Frequency Generator & Integrated Buffers for Celeron & PII/III™& K6 Recommended Application: Motherboard Single chip clock solution for SIS540, SIS630 Pentium II/III and K6 chipsets. Output Features: • 3- CPUs @ 2.5/3.3V, up to 166MHz. • 10 - SDRAM @ 3.3V, up to 166MHz including 2 SDRAM_F's • 7- PCI @3.3V, • 1- 48MHz, @3.3V fixed. • 1- 24/48MHz, @3.3V selectable by I2C (Default is 24MHz). • 2- REF @3.3V, 14.318MHz. Features: • Up to 166MHz frequency support • Support FS0-FS3 trapping status bit for I2C read back. • Support power management: CPU, PCI, SDRAM stop and Power down Mode form I2C programming. • Spread spectrum for EMI control (0 to -0.5%, ± 0.25%). • FS0, FS1, FS3 must have a internal 120K pull-Down to GND. • Uses external 14.

Published: Oct 7, 2005 |