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Integrated Circuit Systems

ICS950810 Datasheet Preview

ICS950810 Datasheet

Frequency Generator with 200MHz Differential CPU Clocks

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Integrated
Circuit
Systems, Inc.
ICS950810
Frequency Generator with 200MHz Differential CPU Clocks
Recommended Application:
CK-408 clock for BANIAS processor/ ODEM and
MONTARA-G chipsets.
Output Features:
• 3 Differential CPU Clock Pairs @ 3.3V
• 7 PCI (3.3V) @ 33.3MHz
• 3 PCI_F (3.3V) @ 33.3MHz
• 1 USB (3.3V) @ 48MHz
• 1 DOT (3.3V) @ 48MHz
• 1 REF (3.3V) @ 14.318MHz
• 5 3V66 (3.3V) @ 66.6MHz
• 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
Features:
• Supports spread spectrum modulation,
down spread 0 to -0.5%. (CPU, 3V66, PCI)
• Efficient power management scheme through PD#,
CPU_STOP# and PCI_STOP#.
Key Specifications:
CPU Output Jitter <150ps
• 3V66 Output Jitter <250ps
• CPU Output Skew <100ps
Pin Configuration
VDDREF 1
X1 2
X2 3
GND 4
PCICLK_F0 5
PCICLK_F1 6
PCICLK_F2 7
VDDPCI 8
GND 9
PCICLK0 10
PCICLK1 11
PCICLK2 12
PCICLK3 13
VDDPCI 14
GND 15
PCICLK4 16
PCICLK5 17
PCICLK6 18
VDD3V66 19
GND 20
3V66_2 21
3V66_3 22
3V66_4 23
3V66_5 24
*PD# 25
VDDA 26
GND 27
Vtt_PWRGD# 28
56 REF
55 FS1
54 FS0
53 CPU_STOP#*
52 CPUCLKT0
51 CPUCLKC0
50 VDDCPU
49 CPUCLKT1
48 CPUCLKC1
47 GND
46 VDDCPU
45 CPUCLKT2
44 CPUCLKC2
43 MULTSEL0*
42 IREF
41 GND
40 FS2
39 48MHz_USB
38 48MHz_DOT
37 VDD48
36 GND
35 3V66_1/VCH_CLK
34 PCI_STOP#*
33 3V66_0
32 VDD3V66
31 GND
30 SCLK
29 SDATA
56-Pin 300mil SSOP
6.10 mm. Body, 0.50 mm. pitch TSSOP
* These inputs have 150K internal pull-up resistor to VDD.
Block Diagram
Functionality
PLL2
X1 XTAL
X2 OSC
PLL1
Spread
Spectrum
PD#
CPU_STOP#
PCI_STOP#
MULTSEL0
FS (2:0)
SDATA
SCLK
Control
Logic
Config.
Reg.
CPU
DIVDER
Stop
PCI
DIVDER
Stop
3V66
DIVDER
48MHz_USB
48MHz_DOT
3V66_5
3V66_3
3V66_(4,2)
REF
3 CPUCLKT (2:0)
3 CPUCLKC (2:0)
PCICLK (6:0)
7
PCICLK_F (2:0)
3
3V66_0
3V66_1/VCH_CLK
I REF
FS2 FS1 FS0
CPU
(MHz)
X0
X0
X1
X1
Mid 0
Mid 0
Mid 1
Mid 1
0
1
0
1
0
1
0
1
166.66
100.00
200.00
133.33
Tristate
TCLK/2
Reserved
Reserved
3V66(5:0)
(MHz)
66.66
66.66
66.66
66.66
Tristate
TCLK/4
Reserved
Reserved
PCI_F
PCI
(MHz)
33.33
33.33
33.33
33.33
Tristate
TCLK/8
Reserved
Reserved
0472F—01/12/04




Integrated Circuit Systems

ICS950810 Datasheet Preview

ICS950810 Datasheet

Frequency Generator with 200MHz Differential CPU Clocks

No Preview Available !

ICS950810
Pin Configuration
PIN
NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PIN NAME
VDDREF
X1
X2
GND
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDDPCI
GND
PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK6
VDD3V66
GND
3V66_2
3V66_3
3V66_4
3V66_5
25 PD#
26 VDDA
27 GND
TYPE
PWR
IN
OUT
PWR
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
IN
PWR
PWR
DESCRIPTION
Ref, XTAL power supply, nominal 3.3V
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Ground pin for 3V outputs.
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Power supply for PCICLK_F and PCICLK, nominal 3.3V
Ground pin for 3V outputs.
PCI clock outputs.
PCI clock outputs.
PCI clock outputs.
PCI clock outputs.
Power supply for PCICLK_F and PCICLK, nominal 3.3V
Ground pin for 3V outputs.
PCI clock outputs.
PCI clock outputs.
PCI clock outputs.
Power pin for the 3V66 clocks.
Ground pin for 3V outputs.
66MHz outputs at 3.3V.
66MHz outputs at 3.3V.
66MHz outputs at 3.3V.
66MHz input/output at 3.3V.
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
3.3V power for the PLL core.
Ground pin for 3V outputs.
0472F—01/12/04
2


Part Number ICS950810
Description Frequency Generator with 200MHz Differential CPU Clocks
Maker Integrated Circuit Systems
Total Page 19 Pages
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