900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf






Integrated Circuit Systems

ICS954101 Datasheet Preview

ICS954101 Datasheet

Programmable Timing Control Hub for Desktop P4 Systems

No Preview Available !

www.DataSheet4U.com
Integrated
Circuit
Systems, Inc.
ICS954101
Programmable Timing Control Hub™ for Desktop P4™ Systems
Recommended Application:
CK410 clock, Intel Yellow Cover part
Output Features:
• 2 - 0.7V current-mode differential CPU pairs
• 6 - 0.7V current-mode differential SRC pair for SATA and
PCI-E
• 1 - 0.7V current-mode differential CPU/SRC selectable
pair
• 6 - PCI (33MHz)
• 3 - PCICLK_F, (33MHz) free-running
• 1 - USB, 48MHz
• 1 - DOT, 96MHz, 0.7V current differential pair
• 1 - REF, 14.318MHz
Features/Benefits:
• Supports tight ppm accuracy clocks for Serial-ATA and
PCI-Express
• Supports spread spectrum modulation, 0 to -0.5%
down spread
• Supports CPU clks up to 400MHz
• Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
• Supports undriven differential CPU, SRC pair in PD#
for power management.
Key Specifications:
• CPU outputs cycle-cycle jitter < 85ps
• SRC output cycle-cycle jitter <125ps
• PCI outputs cycle-cycle jitter < 500ps
• +/- 300ppm frequency accuracy on CPU & SRC clocks
Functionality
FS_C1 FS_B2 FS_A2
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
CPU
SRC
MHz
MHz
266.66 100.00
133.33 100.00
200.00 100.00
166.66 100.00
333.33 100.00
100.00 100.00
400.00 100.00
RESERVED
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
REF
MHz
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
USB
MHz
48.00
48.00
48.00
48.00
48.00
48.00
48.00
48.00
DOT
MHz
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
1. FS_C is a three-level input. Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS_B and FS_A are low-threshold inputs. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
Pin Configuration
VDDPCI 1
GND 2
PCICLK3 3
PCICLK4 4
PCICLK5 5
GND 6
VDDPCI 7
ITP_EN/PCICLK_F0 8
PCICLK_F1 9
PCICLK_F2 10
VDD48 11
USB_48MHz 12
GND 13
DOTT_96MHz 14
DOTC_96MHz 15
FS_B/TEST_MODE 16
Vtt_PwrGd#/PD 17
FS_A_410 18
SRCCLKT1 19
SRCCLKC1 20
VDDSRC 21
SRCCLKT2 22
SRCCLKC2 23
SRCCLKT3 24
SRCCLKC3 25
SRCCLKT4_SATA 26
SRCCLKC4_SATA 27
VDDSRC 28
56 PCICLK2
55 PCICLK1
54 PCICLK0
53 FS_C/TEST_SEL
52 REFOUT
51 GND
50 X1
49 X2
48 VDDREF
47 SDATA
46 SCLK
45 GND
44 CPUCLKT0
43 CPUCLKC0
42 VDDCPU
41 CPUCLKT1
40 CPUCLKC1
39 IREF
38 GNDA
37 VDDA
36 CPUCLKT2_ITP/SRCCLKT_7
35 CPUCLKC2_ITP/SRCCLKC_7
34 VDDSRC
33 SRCCLKT6
32 SRCCLKC6
31 SRCCLKT5
30 SRCCLKC5
29 GND
56-pin SSOP & TSSOP
0815D—06/21/04
DataSheet4 U .com




Integrated Circuit Systems

ICS954101 Datasheet Preview

ICS954101 Datasheet

Programmable Timing Control Hub for Desktop P4 Systems

No Preview Available !

www.DataSheet4U.com
Integrated
Circuit
Systems, Inc.
Pin Description
Pin #
1
2
3
4
5
6
7
VDDPCI
GND
PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
PIN NAME
8 ITP_EN/PCICLK_F0
9 PCICLK_F1
10 PCICLK_F2
11 VDD48
12 USB_48MHz
13 GND
14 DOTT_96MHz
15 DOTC_96MHz
16 FS_B/TEST_MODE
17 Vtt_PwrGd#/PD
18 FS_A_410
19 SRCCLKT1
20 SRCCLKC1
21 VDDSRC
22 SRCCLKT2
23 SRCCLKC2
24 SRCCLKT3
25 SRCCLKC3
26 SRCCLKT4_SATA
27 SRCCLKC4_SATA
28 VDDSRC
ICS954101
PIN TYPE
DESCRIPTION
PWR Power supply for PCI clocks, nominal 3.3V
PWR Ground pin.
OUT PCI clock output.
OUT PCI clock output.
OUT PCI clock output.
PWR Ground pin.
PWR Power supply for PCI clocks, nominal 3.3V
Free running PCI clock not affected by PCI_STOP#.
I/O
ITP_EN: latched input to select pin functionality
1 = CPU_ITP pair
0 = SRC pair
OUT Free running PCI clock not affected by PCI_STOP# .
OUT Free running PCI clock not affected by PCI_STOP# .
PWR Power pin for the 48MHz output.3.3V
OUT 48.00MHz USB clock
PWR Ground pin.
OUT True clock of differential pair for 96.00MHz DOT clock.
OUT Complement clock of differential pair for 96.00MHz DOT clock.
3.3V tolerant input for CPU frequency selection. Refer to input electrical
IN characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time
input to select between Hi-Z and REF/N divider mode while in test mode.
Refer to Test Clarification Table.
Vtt_PwrGd# is an active low input used to determine when latched inputs
IN are ready to be sampled. PD is an asynchronous active high input pin
used to put the device into a low power state. The internal clocks, PLLs
and the crystal oscillator are stopped.
3.3V tolerant low threshold input for CPU frequency selection. This pin
IN requires CK410 FSA. Refer to input electrical characteristics for Vil_FS
and Vih_FS threshold values.
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
PWR Supply for SRC clocks, 3.3V nominal
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
OUT True clock of differential SRC/SATA pair.
OUT Complement clock of differential SRC/SATA pair.
PWR Supply for SRC clocks, 3.3V nominal
0815D—06/21/04
DataSheet4 U .com
2


Part Number ICS954101
Description Programmable Timing Control Hub for Desktop P4 Systems
Maker Integrated Circuit Systems
Total Page 16 Pages
PDF Download

ICS954101 Datasheet PDF

View PDF for Mobile








Similar Datasheet

1 ICS954101 Programmable Timing Control Hub for Desktop P4 Systems
Integrated Circuit Systems





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy