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Integrated Circuit Systems

ICS954201 Datasheet Preview

ICS954201 Datasheet

Programmable Timing Control Hub

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Integrated
Circuit
Systems, Inc.
ICS954201
Programmable Timing Control Hub™ for Mobile P4™ Systems
Recommended Application:
CK410M clock, Intel Yellow Cover part
Output Features:
• 2 - 0.7V current-mode differential CPU pairs
• 7 - 0.7V current-mode differential SRC pair for SATA and
PCI-E
• 1 - 0.7V current-mode differential CPU/SRC selectable
pair
• 4 - PCI (33MHz)
• 2 - PCICLK_F, (33MHz) free-running
• 1 - USB, 48MHz
• 1 - DOT, 96MHz, 0.7V current differential pair
• 1 - REF, 14.318MHz
Features/Benefits:
• Supports tight ppm accuracy clocks for Serial-ATA and
PCI-Express
• Supports spread spectrum modulation, 0 to -0.5%
down spread
• Supports CPU clocks up to 400MHz
• Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
• Supports undriven differential CPU, SRC pair in PD#
for power management.
Key Specifications:
• CPU outputs cycle-cycle jitter < 85ps
• SRC outputs cycle-cycle jitter < 125ps
• PCI outputs cycle-cycle jitter < 500ps
• +/- 300ppm frequency accuracy on CPU & SRC clocks
• +/- 100ppm frequency accuracy on USB clocks
Pin Configuration
VDDPCI 1
GND 2
PCICLK3 3
PCICLK4 4
PCICLK5 5
GND 6
VDDPCI 7
ITP_EN/PCICLK_F0 8
PCICLK_F1 9
Vtt_PwrGd#/PD 10
VDD48 11
USB_48MHz/FS_A 12
GND 13
DOTT_96MHz 14
DOTC_96MHz 15
FS_B/TEST_MODE 16
SRCCLKT0 17
SRCCLKC0 18
SRCCLKT1 19
SRCCLKC1 20
VDDSRC 21
SRCCLKT2 22
SRCCLKC2 23
SRCCLKT3 24
SRCCLKC3 25
SRCCLKT4_SATA 26
SRCCLKC4_SATA 27
VDDSRC 28
Functionality
56 PCICLK2
55 PCI/SRC_STOP#
54 CPU_STOP#
53 FS_C/TEST_SEL
52 REFOUT
FS_C1 FS_B2 FS_A2
0 00
0 01
0 10
0 11
CPU
MHz
266.66
133.33
200.00
166.66
SRC
MHz
100.00
100.00
100.00
100.00
PCI REF
MHz MHz
33.33 14.318
33.33 14.318
33.33 14.318
33.33 14.318
USB
MHz
48.00
48.00
48.00
48.00
DOT
MHz
96.00
96.00
96.00
96.00
51 GND
50 X1
49 X2
48 VDDREF
1 0 0 333.33 100.00 33.33 14.318 48.00 96.00
1 0 1 100.00 100.00 33.33 14.318 48.00 96.00
1 1 0 400.00 100.00 33.33 14.318 48.00 96.00
1 11
RESERVED
14.318 48.00 96.00
47 SDATA
46 SCLK
45 GND
44 CPUCLKT0
43 CPUCLKC0
1. FS_C is a three-level input. Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS_B and FS_A are low-threshold inputs. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
42 VDDCPU
41 CPUCLKT1
40 CPUCLKC1
39 IREF
38 GNDA
37 VDDA
36 CPUCLKT2_ITP/SRCCLKT7
35 CPUCLKC2_ITP/SRCCLKC7
34 VDDSRC
33 SRCCLKT6
32 SRCCLKC6
31 SRCCLKT5
30 SRCCLKC5
29 GND
56-pin SSOP & TSSOP
0819G—12/06/04
DataSheet4 U .com




Integrated Circuit Systems

ICS954201 Datasheet Preview

ICS954201 Datasheet

Programmable Timing Control Hub

No Preview Available !

www.DataSheet4U.com
Integrated
Circuit
Systems, Inc.
Pin Description
PIN # PIN NAME
1 VDDPCI
2 GND
3 PCICLK3
4 PCICLK4
5 PCICLK5
6 GND
7 VDDPCI
8 ITP_EN/PCICLK_F0
9 PCICLK_F1
10 Vtt_PwrGd#/PD
11 VDD48
12 USB_48MHz/FS_A
13 GND
14 DOTT_96MHz
15 DOTC_96MHz
16 FS_B/TEST_MODE
17 SRCCLKT0
18 SRCCLKC0
19 SRCCLKT1
20 SRCCLKC1
21 VDDSRC
22 SRCCLKT2
23 SRCCLKC2
24 SRCCLKT3
25 SRCCLKC3
26 SRCCLKT4_SATA
27 SRCCLKC4_SATA
28 VDDSRC
ICS954201
PIN
TYPE
PWR
PWR
OUT
OUT
OUT
PWR
PWR
I/O
OUT
IN
PWR
I/O
PWR
OUT
DESCRIPTION
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin.
Power supply for PCI clocks, nominal 3.3V
Free running PCI clock not affected by PCI_STOP#.
ITP_EN: latched input to select pin functionality
1 = CPU_ITP pair
0 = SRC pair
Free running PCI clock not affected by PCI_STOP# .
Vtt_PwrGd# is an active low input used to determine when
latched inputs are ready to be sampled. PD is an asynchronous
active high input pin used to put the device into a low power
state. The internal clocks, PLLs and the crystal oscillator are
stopped.
Power pin for the 48MHz output.3.3V
Frequency select latch input pin / Fixed 48MHz USB clock
output. 3.3V.
Ground pin.
True clock of differential pair for 96.00MHz DOT clock.
OUT Complement clock of differential pair for 96.00MHz DOT clock.
IN
OUT
OUT
OUT
OUT
PWR
OUT
OUT
OUT
OUT
OUT
OUT
PWR
3.3V tolerant input for CPU frequency selection. Refer to input
electrical characteristics for Vil_FS and Vih_FS values.
TEST_MODE is a real time input to select between Hi-Z and
REF/N divider mode while in test mode. Refer to Test
Clarification Table.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
Supply for SRC clocks, 3.3V nominal
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC/SATA pair.
Complement clock of differential SRC/SATA pair.
Supply for SRC clocks, 3.3V nominal
0819G—12/06/04
DataSheet4 U .com
2


Part Number ICS954201
Description Programmable Timing Control Hub
Maker Integrated Circuit Systems
Total Page 15 Pages
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