M2020 - VCSO BASED CLOCK PLL

Integrated Circuit Systems

M2020 Datasheet Preview — Preview of M2020 PDF

Datasheet Details

Part number	M2020
Manufacturer	Integrated Circuit Systems
File Size	431.78 KB
Description	VCSO BASED CLOCK PLL
Datasheet	M2020_IntegratedCircuitSystems.pdf

M2020 Product details

Description

The M2020/21 is a VCSO (Voltage Controlled SAW Oscillator) based clock jitter attenuator PLL designed for clock jitter attenuation and frequency translation.

Features

Integrated SAW (surface acoustic wave) delay line; low phase jitter of < 0.5ps rms, typical (12kHz to 20MHz or 50kHz to 80MHz).
Output frequencies of 15 to 700 MHz.
LVPECL clock output (CML and LVDS options available).
Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL.
Loss of Lock (LOL) output pin.
Narrow Bandwidth control input (NBW pin).
Hitless Switching (HS) options with or without Phase Build-out (PBO).

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Published: Mar 30, 2005 |