MK2049-45 - 3.3V Communications Clock PLL

Integrated Circuit Systems

Datasheet Details

Part number	MK2049-45
Manufacturer	Integrated Circuit Systems
File Size	212.72 KB
Description	3.3V Communications Clock PLL
Datasheet	MK2049-45_IntegratedCircuitSystems.pdf

The MK2049-45 is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation.

Packaged in 20 pin SOIC.
3.3 V + 5% operation.
Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz Locks to 8 kHz + 100 ppm (External mode) Buffer Mode allows jitter attenuation of 10 - 50 MHz input and x1 / x0.5 or x1 / x2 outputs Exact internal ratios enable zero ppm error Output rates include T1, E1,.

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Published: Apr 7, 2011 |