| Part Number | MK2049-45 Datasheet |
|---|---|
| Manufacturer | Integrated Circuit Systems |
| Overview |
The MK2049-45 is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and .
* Packaged in 20 pin SOIC * 3.3 V + 5% operation * Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz Locks to 8 kHz + 100 ppm (Exte. |
MK2049-45 Datasheet and Specifications PDF
The MK2049-45 is a 3.3V Communications Clock PLL.
| Part Number | MK2049-45 Datasheet |
|---|---|
| Description | CLOCK PLL |
| Manufacturer | Renesas |
| Overview |
The MK2049-45A is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and.
* Packaged in 20-pin SOIC * 3.3 V + 5% operation * Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E * Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz * Locks to 8 kHz + 100 ppm (. |
| Part Number | MK2049-45 Datasheet |
|---|---|
| Description | CLOCK PLL |
| Manufacturer | Renesas |
| Overview |
The MK2049-45 is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and .
* Packaged in 20 pin SOIC * 3.3 V + 5% operation * Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E * Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz * Locks to 8 kHz + 100 ppm (. |